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US 7,733,734 B2Granted
Semiconductor memory device with control block sharing row decoders
AssigneeHynix Semiconductor Inc.
InventorWoo-Seok Song
Life of this patent
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Abstract
A semiconductor memory device comprises a plurality of banks including a plurality of mat rows, respectively, wherein the mat row includes a plurality of mats disposed in a same row, row decoder groups disposed between the banks and including row decoders that correspond to the mat rows, respectively, and common control blocks installed corresponding to a predetermined number of row decoders to simultaneously control the row decoders.
Claims25
A semiconductor memory device comprising:
- a plurality of banks including a plurality of mat rows, respectively, wherein each of the plurality of mat rows includes a plurality of mats;
- a plurality of row decoder groups disposed between the plurality of banks and each of the plurality of row decoder groups including row decoders that correspond to the mat rows;
- and
- a plurality of common control blocks corresponding to a predetermined number of row decoders and configured to simultaneously control the predetermined number of the row decoders,
- wherein the plurality of common control blocks are allocated per one bank.
2 more elements
A semiconductor memory device comprising:
- a plurality of bank, each of the plurality of bank including a plurality of mat rows, wherein each of the plurality of mat rows includes a plurality of mats;
- a plurality of row decoder groups corresponding to the mat rows and each of the plurality of row decoder groups including a plurality of row decoders that selectively drive word lines of each of the plurality of mat rows;
- a row address latch block configured to generate a row address latch enable signal for driving the word lines, and a multi row address latch enable signal that groups the plurality of mat rows and the plurality of row decoders into a plurality of mat row blocks including a predetermined number of mat rows and a plurality of row decoder blocks including a predetermined number of row decoders, respectively;
- and
- a plurality of common control blocks corresponding to the plurality of row decoder blocks and configured to generate a mat block selection signal, which selects one of the mat row blocks, and a row decoder block selection signal, which selects one of the row decoder blocks, by using the multi row address latch enable signal.
2 more elements
Dependencies are inferred from the claim text.