Negative voltage detection circuit and semiconductor integrated circuit

A semiconductor integrated circuit comprising:

• a reference voltage generating circuit configured to generate a reference voltage;
• a positive voltage generating circuit configured to generate a positive polarity voltage on the basis of the reference voltage generated in the reference voltage generating circuit;
• a negative voltage generation circuit configured to generate a negative polarity voltage on the basis of the reference voltage generated in the reference voltage generating circuit, said negative voltage generation circuit further includes an oscillation circuit and a negative voltage boost circuit, wherein said negative voltage boost circuit is supplied with an oscillation output of the oscillation circuit, to generate the negative polarity voltage;
• a voltage switching circuit supplied with the positive polarity voltage generated in the positive voltage generating circuit and the negative polarity voltage generated in the negative voltage generating circuit, and configured to select and output either of the negative polarity voltage or the positive polarity voltage;
• a memory cell array configured to receive either the positive polarity voltage or the negative polarity voltage selected by the voltage switching circuit;
• a row decoder configured to receive either the positive polarity voltage or the negative polarity voltage selected by the voltage switching circuit;
• and
• a column decoder/sense amplifier configured to receive either the positive polarity voltage or the negative polarity voltage selected by the voltage switching circuit;
• and
• a negative voltage detection circuit configured to detect the negative polarity voltage generated in the negative voltage boost circuit to control the oscillation operation of the oscillation circuit, said negative voltage detection circuit including
• a detection circuit configured to detect at least one of a temperature or a power supply voltage, generate a control signal corresponding to the detection result, and output said control signal;
• a first MOS transistor circuit in which a first end of a current path is coupled to a supply node of a power supply voltage, said first MOS transistor circuit being configured to change a dimension size of a transistor on the basis of the control signal;
• a resistance including a first resistive end and a second resistive end, said first resistive end being coupled to a second end of the current path of the first MOS transistor circuit, and said second resistive end being coupled to a supply node of a ground potential;
• a first comparator circuit configured to compare a first voltage generated at the first resistive end of the resistance with a reference voltage, and to control a gate electrode of the first MOS transistor circuit;
• a second MOS transistor circuit in which a first end of a current path is coupled to a supply node of a power supply voltage, said second MOS transistor circuit being configured to change a dimension size of a transistor on the basis of the control signal, said second MOS transistor circuit further including a gate electrode commonly coupled to a gate electrode of the first MOS transistor circuit so as to form a current mirror circuit together with the first MOS transistor circuit;
• a resistive divider including a first resistive end and a second resistive end, said first resistive end being configured to receive a negative voltage to be detected, and said second resistive end being coupled to a second end of the current path of the second MOS transistor circuit to generate a second voltage;
• and
• a second voltage comparator circuit configured to compare the second voltage with a reference voltage to generate a detection signal corresponding to the value of the negative voltage.