Controlling global bit line pre-charge time for high speed eDRAM

A method of operating a memory, the method comprising:

• generating a global bit line (GBL) pre-charge signal for a write operation (GEQ_write signal) on a first node of the memory;
• using the GEO write signal to start a first GBL pre-charge;
• generating a GBL pre-charge signal for a read operation (GEQ_read signal) on a second node of the memory, wherein the second node is different from the first node, and wherein the second node does not carry the GEQ_write signal;
• and
• using the GEQ_read signal to start a second GBL pre-charge, wherein the GEQ_write signal and the GEQ_read signal are NORed to control the first GBL pre-charge and the second GBL pre-charge.

A method of operating a memory, the method comprising:

• generating a global bit line (GBL) pre-charge signal for a write operation (GEQ_write signal) on a first node of the memory;
• applying the GEQ_write signal to the memory to start a first GBL pre-charge to a GBL;
• writing into a memory cell controlled by the GBL, wherein the steps of starting the first GBL pre-charge and writing into the memory cell have a first time interval;
• generating a GBL pre-charge enable signal for a read operation (GEQ_read signal) on a second node of the memory, wherein the second node is different from the first node;
• applying the GEQ_read signal to the memory to start a second GBL pre-charge;
• and
• reading from the memory cell, wherein the steps of starting the second GBL pre-charge and reading from the memory cell have a second time interval smaller than the first time interval.

A memory circuit comprising:

• a global bit line (GBL) pre-charge signal generator comprising:
• a first output node outputting a GBL pre-charge signal for a write operation (GEQ_write signal);
• a second output node outputting a GBL pre-charge signal for a read operation (GEQ_read signal), wherein the second output node does not output the GEQ_write signal;
• and
• a third output node outputting a write enable signal.

A memory circuit comprising:

• a local bit line (LBL);
• a global bit line (GBL);
• a multiplexer (MUX) coupling the LBL and the GBL;
• and
• a MUX signal generator comprising:
• a first input node coupled to a write enable signal node;
• a second input node coupled to a local sensing activation enable signal node;
• and
• an output node coupled to the MUX.

A memory circuit comprising:

• a first and a second local bit line (LBL);
• a first and a second global bit line (GBL);
• a multiplexer (MUX) coupling the first LBL to the first GBL, and the second LBL to the second GBL;
• a GBL pre-charge signal generator comprising:
• a first output node outputting a GBL pre-charge signal for a write operation (GEQ_write signal);
• a second output node outputting a GBL pre-charge enable signal for a read operation (GEQ_read signal);
• and
• a third output node outputting a write enable signal;
• a MUX signal generator comprising:
• a first input coupled to the third output node of the GBL pre-charge signal generator;
• a second input node coupled to a local sensing activation enable signal node;
• and
• an output node coupled to the MUX;
• and
• a NOR gate comprising:
• a first input coupled to the first output node of the GBL pre-charge signal generator;
• a second input coupled to the second output node of the GBL pre-charge signal generator;
• and
• an output coupled to an equalization circuit coupled between the first and the second GBLs.