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US 7,733,723 B2Granted
Semiconductor memory device having precharge signal generator and its driving method
AssigneeHynix Semiconductor Inc.
InventorSun-Suk Yang
Life of this patent
Estimating the term…
Abstract
A semiconductor memory device includes a drive clock supplier and a signal generator. The drive clock supplier supplies a drive clock which is obtained by dividing an internal clock with a divide ratio, wherein the drive clock synchronizes with a rising edge of the internal clock with which an internal write signal synchronizes. The signal generator counts time corresponding to a write-recovery on the basis of the drive clock, to generate a precharge signal.
Claims25
A semiconductor memory device comprising:
- a selection signal generator configured to receive an internal write signal and generate a selection signal;
- a clock divider configured to receive and divide an internal clock and generate a plurality of divided clocks;
- a drive clock supplier configured to supply one of the plurality of divided clocks as a drive clock in response to the selection signal, wherein the selection signal indicates which one of the plurality of divided clocks is synchronized with the internal write signal;
- a write interval signal generator configured to receive the internal write signal and a column address and generate a write interval signal;
- and
- a signal generator configured to determine a delay time corresponding to a write-recovery time in response to the drive clock supplied from the drive clock supplier and a write-recovery information signal representing the write-recovery time and to generate a precharge signal by delaying the write interval signal for the delay time.
3 more elements
A semiconductor memory device comprising:
- a divider configured to divide an internal clock to generate first and second divided clocks with different phases;
- and
- a selection controller configured to generate a selection signal representing whether an internal write signal synchronizes with the first divided clock or the second divided clock;
- a drive clock selector configured to provide one of the first and the second divided clocks as a drive clock in response to the selection signal;
- and
- a signal generator configured to generate a write interval signal based on the internal write signal and a column address and produce a precharge signal by delaying the write interval signal for a delay time corresponding to a write-recovery time from an activation of the internal write signal based on the drive clock.
3 more elements
A driving method of a semiconductor memory device, comprising:
- dividing an internal clock into first and second divided clocks each having a different phase;
- supplying one of the first and second divided clocks as a drive clock based on an internal write signal;
- and
- generating a write interval signal based on the internal write signal and a column address;
- generating a precharge signal by delaying the write interval signal for a delay time corresponding to a write-recovery time from the internal write signal based on the drive clock.
2 more elements
Dependencies are inferred from the claim text.