Method and system of analyzing failure in semiconductor integrated circuit device

A method of analyzing a failure in a semiconductor integrated circuit device, the method comprising:

• performing defect inspection on a first wafer in the course of a production process of the first wafer to detect a defect in the first wafer;
• after completing formation of the first wafer, performing an electrical test on the first wafer to detect a defective SRAM cell in the first wafer;
• measuring the analog characteristics of a defective SRAM cell in the first wafer;
• verifying whether the defect in the first wafer is correlated with the analog characteristics of the defective SPAM cell;
• storing in the database information on the defect in the first wafer and the measured analog characteristics, which have been verified as being correlated with each other;
• performing an electrical test on a second wafer after completing production of the second wafer to detect a defective SRAM cell in the second wafer;
• measuring the analog characteristics of the defective SPAM cell in the second wafer;
• and
• identifying the defect that has caused the defective SRAM cell by comparing the measured analog characteristics with the stored analog characteristics.

A system of analyzing a failure in a semiconductor integrated circuit device, the system comprising:

• a database storing defects and analog characteristics correlated with the defects;
• an electrical tester that detects a fail bit in a wafer;
• an analog characteristic tester that measures analog characteristics of the fail bit in the wafer;
• and
• an analyzer that identifies the defect that has caused the fail bit by comparing the measured analog characteristics with the stored analog characteristics, wherein one or more kinds of defects are correlated with the analog characteristics of the fail bit.