MIS-transistor-based nonvolatile memory for multilevel data storage
AssigneeNSCore Inc.
InventorsTadahiko Horiuchi, Kenji Noda
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Abstract
A memory circuit includes a latch having a first node and a second node to store data such that a logic level of the first node is an inverse of a logic level of the second node, a MIS transistor having a gate node, a first source/drain node, and a second source/drain node, the first source/drain node coupled to the first node of the latch, and a control circuit configured to control the gate node and second source/drain node of the MIS transistor to make an upward lingering change in a threshold voltage of the MIS transistor in a first operation in response to data stored in the latch and to make a downward lingering change in the threshold voltage in a second operation in response to data stored in the latch.
Claims10
A memory circuit, comprising:
- a latch having a first node and a second node to store data such that a logic level of the first node is an inverse of a logic level of the second node;
- a MIS transistor having a gate node, a first source/drain node, and a second source/drain node, the first source/drain node coupled to the first node of the latch;
- and
- a control circuit configured to control the gate node and second source/drain node of the MIS transistor to make an upward lingering change in a threshold voltage of the MIS transistor in a first operation in response to data stored in the latch and to make a downward lingering change in the threshold voltage in a second operation in response to data stored in the latch, the upward lingering change being a shift of the threshold voltage from an initial threshold in a first direction and the downward lingering change being a shift of the threshold voltage from the initial threshold in a second direction opposite the first direction.
A memory circuit, comprising:
- a latch having a first node and a second node to store data such that a logic level of the first node is an inverse of a logic level of the second node;
- a MIS transistor having a gate node, a first source/drain node, and a second source/drain node, the first source/drain node coupled to the first node of the latch;
- and
- a control circuit configured to control the gate node and second source/drain node of the MIS transistor to make an upward lingering change in a threshold voltage of the MIS transistor in a first operation in response to data stored in the latch and to make a downward lingering change in the threshold voltage in a second operation in response to data stored in the latch, wherein the control circuit is further configured to control the gate node and second source/drain node of the MIS transistor in a third operation to cause the latch to store data responsive to a comparison between a drain current running through the MIS transistor and a reference current.
A memory circuit, comprising:
- a latch having a first node and a second node to store data such that a logic level of the first node is an inverse of a logic level of the second node;
- a MIS transistor having a gate node, a first source/drain node, and a second source/drain node, the first source/drain node coupled to the first node of the latch;
- a control circuit configured to control the gate node and second source/drain node of the MIS transistor to make an upward lingering change in a threshold voltage of the MIS transistor in a first operation in response to data stored in the latch and to make a downward lingering change in the threshold voltage in a second operation in response to data stored in the latch;
- and
- switch circuits configured to change electrical connections for the first source/drain node and second source/drain node of the MIS transistor to provide a first connection mode and a second connection mode, such that the first source/drain node serves as a drain node during the first operation and second operation in the first connection mode while the second source/drain node serves as a drain node during the first operation and second operation in the second connection mode.
Dependencies are inferred from the claim text.