Storage subsystem with embedded circuit for protecting against anomalies in power signal from host

A storage subsystem, comprising:

• a controller that writes data to, and reads data from, a non-volatile storage medium;
• a charge pump circuit that receives a power signal from a host system and generates a regulated power signal that is provided to the controller, wherein the charge pump circuit is capable of maintaining the regulated power signal to the controller when the power signal from the host system is interrupted;
• an isolation circuit that substantially prevents power in the controller from flowing back to the host system when the power signal from the host system is interrupted, whereby the power is preserved in the controller to complete outstanding memory operations, the isolation circuit comprising:
• a low dropout regulator;
• a voltage input connected to an input terminal and an enable terminal of the low dropout regulator;
• and
• at least one input capacitor connected between the voltage input and ground;
• and
• a voltage detection circuit that monitors the power signal from the host system to detect anomalies therein, and responds to detection of such an anomaly by asserting a busy signal to the controller.

A storage subsystem, comprising:

• a controller that writes data to, and reads data from, a non-volatile storage medium;
• a charge pump circuit that receives a power signal from a host system and generates a regulated power signal that is provided to the controller, wherein the charge pump circuit is capable of maintaining the regulated power signal to the controller when the power signal from the host system is interrupted;
• an isolation circuit that substantially prevents power in the controller from flowing back to the host system when the power signal from the host system is interrupted, whereby the power is preserved in the controller to complete outstanding memory operations;
• and
• a voltage detection circuit that monitors the power signal from the host system to detect anomalies therein, and responds to detection of such an anomaly by asserting a busy signal to the controller,
• wherein the isolation circuit comprises an opt-isolator.

A storage subsystem, comprising:

• a controller that writes data to, and reads data from, a non-volatile storage medium;
• a charge pump circuit that receives a power signal from a host system and generates a regulated power signal that is provided to the controller, wherein the charge pump circuit is capable of maintaining the regulated power signal to the controller when the power signal from the host system is interrupted;
• an isolation circuit that substantially prevents power in the controller from flowing back to the host system when the power signal from the host system is interrupted, whereby the power is preserved in the controller to complete outstanding memory operations;
• and
• a voltage detection circuit that monitors the power signal from the host system to detect anomalies therein, and responds to detection of such an anomaly by asserting a busy signal to the controller, the voltage detection circuit comprising:
• a voltage detector;
• a voltage input;
• a voltage divider comprising at least one resistor, wherein the voltage divider is located between the voltage input and the voltage detector;
• a input capacitor connected across the voltage input and to the voltage detector and ground;
• and
• at least one resistor connected between the voltage detector and a voltage output.

A memory subsystem that protects against data losses caused by power signal anomalies, the memory subsystem comprising:

• a solid state non-volatile memory array;
• a controller that transfers data between a host system and the solid state non-volatile memory array, the controller comprising a logic unit;
• a regulation circuit that receives a power signal from the host system, and generates a regulated power signal that is provided to the controller;
• an isolation circuit that substantially prevents power in the controller from flowing back to the host system in the event of an anomaly in the power signal, whereby the power is preserved in the controller to complete outstanding memory operations;
• and
• a voltage detection circuit that monitors the power signal from the host system to detect anomalies therein, wherein the voltage detection circuit responds to detection of the anomaly in the power signal by causing a busy signal to be asserted to the logic unit of the controller, wherein the busy signal asserted to the logic unit causes the controller to assert a busy signal to the host system to block the host system from performing write operations to the memory subsystem during presence of the anomaly.

A memory subsystem that protects against data losses caused by power signal anomalies, the memory subsystem comprising:

• a solid state non-volatile memory array;
• a controller that transfers data between a host system and the solid state non-volatile volatile memory array, the controller comprising a logic unit;
• a regulation circuit that receives a power signal from the host system, and generates a regulated power signal that is provided to the controller;
• an isolation circuit that substantially prevents power in the controller from flowing back to the host system in the event of an anomaly in the power signal, whereby the power is preserved in the controller to complete outstanding memory operations;
• and
• a voltage detection circuit that monitors the power signal from the host system to detect anomalies therein, wherein the voltage detection circuit responds to detection of the anomaly in the power signal by causing a busy signal to be asserted to the logic unit of the controller,
• wherein the isolation circuit comprises an opt-isolator.

A memory subsystem that protects against data losses caused by power signal anomalies, the memory subsystem comprising:

• a solid state non-volatile memory array;
• a controller that transfers data between a host system and the solid state non-volatile volatile memory array, the controller comprising a logic unit;
• a regulation circuit that receives a power signal from the host system, and generates a regulated power signal that is provided to the controller;
• an isolation circuit that substantially prevents power in the controller from flowing back to the host system in the event of an anomaly in the power signal, whereby the power is preserved in the controller to complete outstanding memory operations;
• and
• a voltage detection circuit that monitors the power signal from the host system to detect anomalies therein, wherein the voltage detection circuit responds to detection of the anomaly in the power signal by causing a busy signal to be asserted to the logic unit of the controller, the voltage detection circuit comprising a voltage divider.

A method of responding to anomalies in a power signal provided by a host system to a storage subsystem, the method comprising, with the storage subsystem:

• receiving the power signal from the host system, the host system being separate from the storage subsystem and pluggably connecting to the storage subsystem;
• detecting an anomaly in the power signal with a detection circuit of the storage subsystem;
• in response to detection of the anomaly by the detection circuit, asserting a signal to a controller of the storage subsystem to cause the controller to forward a signal to the host system to inhibit the host system from writing data to the storage subsystem during presence of the anomaly;
• and
• during the presence of the anomaly, substantially preventing power from being drained from the storage subsystem toward the host system with a power isolation circuit, whereby the power is preserved on the storage subsystem to complete outstanding memory operations.