US 7,733,711 B2 · Circuit and method for optimizing memory sense amplifier timing

Abstract

A memory has an array of memory cells, a word line driver, a sense amplifier, and a sense enable circuit. Each memory cell has a coupling transistor for coupling a storage portion to a bit line. The coupling transistors have an average threshold voltage and a maximum threshold voltage. The word line driver is coupled to the array and is for enabling a selected row of memory cells in the array. The sense amplifier detects a state of a memory cell in the selected row in response to a sense enable signal. The sense enable circuit provides the sense enable signal at a time based on the maximum threshold voltage. This timing enables the sense amplifier sufficiently late for low temperature operation while providing for faster operation at high temperature than would normally be achieved using just the average threshold voltage in providing timing of the sense enable signal.

Claims20

Dependent claims

A memory comprising:

an array of memory cells, wherein each memory cell comprises a coupling transistor for coupling a storage portion to a bit line, wherein a statistical average of threshold voltages of coupling transistors within the array is an average threshold voltage and at least one coupling transistor has a maximum possible threshold voltage;
a word line driver coupled to the array for enabling a selected row of memory cells in the array;
a sense amplifier for detecting a state of a memory cell in the selected row in response to a sense enable signal;
and
a sense enable circuit for providing the sense enable signal at a time based on the maximum possible threshold voltage.

2 more elements

A memory comprising:

an array of memory cells:
a word line driver coupled to the array for enabling a selected row of memory cells in the array;
a sense amplifier for detecting a state of a memory cell in the selected row in response to a sense enable signal;
and
a sense enable circuit for providing the sense enable signal at a time based on a maximum possible threshold voltage of predetermined transistors in the array of memory cells, wherein the sense enable circuit comprises:
a first resistor having a first terminal as a first terminal of a voltage divider and a second terminal;
a second resistor having a first terminal coupled to the second terminal of the first resistor and a second terminal as a second terminal of the voltage divider comprising the first resistor and the second resistor, wherein the second terminal of the first resistor and the first terminal of the second resistor form an output of the voltage divider;
a first delay circuit having an input responsive to a word line enable signal and an output;
a first transistor having a first current electrode coupled to a first power supply terminal, a control electrode coupled to the output of the first delay circuit, and a second current electrode coupled to the first terminal of the voltage divider;
and
a second delay circuit characterized as modeling a bit line and a memory cell having an input coupled to the output of the voltage divider and an output that provides the sense enable signal.

8 more elements

Dependencies are inferred from the claim text.

Circuit and method for optimizing memory sense amplifier timing

Life of this patent

Circuit and method for optimizing memory sense amplifier timing

Life of this patent

Abstract

Claims20