Reduction of punch-through disturb during programming of a memory device
AssigneeMicron Technology, Inc.
InventorsAlessandro Torsi, Carlo Musilli, Seiichi Aritome
Life of this patent
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Abstract
A punch-through disturb effect in a memory device can be reduced by biasing a selected word line at a program voltage to program a selected memory cell, biasing word lines on the drain side of the series string with a Vpass voltage, turning off an adjacent memory cell to the selected memory cell, and biasing remaining word lines on the source side of the turned-off memory cell with a Vlow voltage that is less than Vpass.
Claims20
A method for reducing punch-through effect during a programming operation in a memory device, the method comprising:
- biasing a control gate of a selected memory cell with a program voltage;
- biasing control gates of unselected memory cells on a drain-side of the selected memory cell with a Vpass voltage;
- and
- biasing control gates of unselected memory cells on a source-side of the selected cell with a Vlow voltage that is less than the Vpass voltage.
A method for reducing punch-through effect during programming of a memory block in a non-volatile memory device, the method comprising:
- biasing a selected word line of a series string with at least one programming pulse at an initial programming voltage;
- biasing, with a first voltage, a first unselected word line on a drain-side of and adjacent to the selected word line and a second unselected word line on a source-side of and adjacent to the selected word line;
- biasing remaining unselected word lines on the drain-side of the selected word line at Vpass that is greater than the first voltage;
- biasing a third unselected word line, adjacent to the second adjacent word line, at ground potential;
- and
- biasing remaining unselected word lines on the source-side of the third unselected word line at Vlow that is less than both Vpass and the first voltage.
A method for reducing punch-through effect during programming of a memory block in a non-volatile memory device, the method comprising:
- biasing a selected word line of a series string of memory cells with at least one programming pulse at an initial programming voltage;
- biasing, with a first voltage, a first unselected word line on a source-side of and adjacent to the selected word line;
- biasing unselected word lines on the drain-side of the selected word line at Vpass that is greater than the first voltage;
- biasing a second unselected word line, adjacent to the first adjacent word line, at ground potential;
- and
- biasing remaining unselected word lines on the source-side of the second unselected word line at Vlow, that is less than both Vpass and the first voltage.
A method for reducing punch-through effect during programming of a memory block in a non-volatile memory device, the method comprising:
- biasing a selected word line of a series string of memory cells with a programming pulse at a programming voltage;
- biasing, at a Vpass voltage, a first unselected word line on a source-side of and adjacent to the selected word line;
- biasing unselected word lines on the drain-side of the selected word line at the Vpass voltage;
- biasing, at a first voltage that is less than the Vpass voltage, a second unselected word line on the source-side of and adjacent to the first unselected word line;
- biasing, at ground potential, a third unselected word line, adjacent to and on the source-side of the second unselected word line;
- and
- biasing, at Vlow that is less than both Vpass and the first voltage, remaining unselected word lines on the source-side of the third unselected word line.
A non-volatile memory device comprising:
- an array of memory cells wherein rows of memory cells are coupled to word lines and series strings of memory cells are coupled to bit lines;
- and
- memory control circuitry coupled to the array of memory cells and adapted to perform a programming operation on a target memory cell that includes a self-boost operation to reduce punch-through disturb in response to a bias on a selected word line with a program voltage, a bias on unselected word lines on a drain-side of the selected word line with a Vpass voltage, and a bias on unselected word lines on a source-side of the selected word line with a Vlow voltage that is less than the Vpass voltage.
Dependencies are inferred from the claim text.