Method and structures for highly efficient hot carrier injection programming for non-volatile memories

Structure for programming a metal oxide semiconductor field effect transistor (MOSFET) in a non-volatile memory cell, said transistor having a source, a drain, a channel region between the source and the drain, and a control gate over but separated by dielectric and a charge storage region in said dielectric from said channel region, said source, drain and channel region being formed in a substrate of opposite conductivity type to the conductivity type of said source and said drain;

• said structure comprising:
• means for connecting the drain electrode of said MOSFET to a supply source of the main voltage, or ground, provided to said non-volatile memory cell;
• means for supplying selected voltages to said source, said substrate and said control gate thereby to invert a portion of the channel region extending from the source toward the drain, the inverted portion of the channel region ending at a pinch-off point before reaching the drain;
• and
• means for reverse biasing the PN junction between the source and the substrate to pull the pinch-off point of the inversion region back toward the source thereby to optimize the programming efficiency of the MOSFET.

A method for programming an N-type metal oxide semiconductor field effect transistor (MOSFET) in a non-volatile memory cell, said transistor having a source, a drain and a channel region between the source and the drain, said transistor further having a control gate formed over dielectric above said channel region and a charge storage region formed in said dielectric, said source, drain and channel region being formed in a substrate of opposite conductivity type to the conductivity type of said source and said drain, said method comprising:

• applying a first voltage to said drain electrode;
• applying to said control gate a second voltage greater than said first voltage so as to form in said channel region an inversion region extending from the source toward the drain, the second voltage being selected so that the inversion region ends at a pinch-off point before reaching the drain;
• and
• reverse biasing the PN junction between the source and substrate to a selected value by applying a third voltage to said source and a fourth voltage to said substrate, said third voltage being less than said first voltage and more than said fourth voltage, thereby together with said second voltage causing said pinch-off point to be located at a point between the source and the drain so as to improve the programming efficiency of the MOSFET;
• wherein the difference between said first voltage and said fourth voltage is capped to be below the avalanche multiplication junction breakdown voltage.

Structure for programming a metal oxide semiconductor field effect transistor (MOSFET) in a non-volatile memory cell, said transistor having a source, a drain, a channel region between the source and the drain, and a control gate over but separated by dielectric from said channel region, and a charge storage region in said dielectric, said source, drain and channel region being formed in a substrate of opposite conductivity type to the conductivity type of said source and said drain;

• said structure comprising:
• means for supplying a first voltage to the drain electrode of said MOSFET;
• means for supplying a second voltage to said control gate, a third voltage to said source and a fourth voltage to said substrate, thereby to invert a portion of the channel region extending from the source toward the drain, the inverted portion of the channel region ending at a pinch-off point before reaching the drain;
• and
• means for controlling the reverse bias across the PN junction between the source and the substrate by controlling the values of said third voltage and said fourth voltage to pull the pinch-off point of the inversion region back toward the source thereby to improve the programming efficiency of the MOSFET;
• wherein said fourth voltage differs from said first voltage by an amount less than the avalanche breakdown junction voltage of the PN junction between said drain and said substrate.