Non-volatile memory devices including local control gates on multiple isolated well regions and related methods and systems

An electronic system comprising:

• a semiconductor substrate including first and second electrically isolated wells having a same conductivity type;
• a first plurality of non-volatile memory cell transistors on the first well;
• a second plurality of non-volatile memory cell transistors on the second well;
• a local control gate line electrically coupled with the first and second pluralities of non-volatile memory cell transistors;
• and
• a single group selection transistor electrically coupled between the local control gate line and a global control gate line, wherein the single group selection transistor is commonly coupled with the first and second pluralities of non-volatile memory cell transistors through the local control gate line and configured to electrically couple and decouple the local control gate line and the global control gate line responsive to a group selection gate signal applied to a gate of the single group selection transistor,
• wherein the first well and the second well are biased with different voltages to selectively erase either the first plurality of non-volatile memory cell transistors or the second plurality of non-volatile memory cell transistors during an erase operation while applying a same control gate signal from the global control gate line through the single group selection transistor and the local control gate line to the first and second pluralities of non-volatile memory cell transistors respectively on the first and second electrically isolated wells.