Non-volatile memory device and method of operation therefor
AssigneeSamsung Electronics Co., Ltd.
InventorsDae-Yong Kim, Sang-Won Hwang, Jun-Yong Park
Life of this patent
Estimating the term…
Abstract
In one embodiment, the non-volatile memory device includes a well of a first conductivity type formed in a substrate, and a first plurality of memory cell transistors connected in series to a bit line formed in the well. A buffer is formed in the substrate outside the well and is connected to the bit line. At least one de-coupling transistor is configured to de-couple the buffer from the bit line, and the de-coupling transistor is formed in the well.
Claims15
A non-volatile memory device, comprising:
- a well of a first conductivity type formed in a substrate;
- a first plurality of memory cell transistors connected in series to a bit line and formed in the well;
- a buffer formed in the substrate outside the well and connected to the bit line;
- at least one de-coupling transistor configured to de-couple the buffer from the bit line, the de-coupling transistor being formed in the well;
- and
- a blocking transistor connected to the de-coupling transistor and formed outside the well, the blocking transistor configured to selectively cut off the buffer from the bit line.
A non-volatile memory device, comprising:
- a well of a first conductivity type formed in a substrate;
- a first plurality of memory cell transistors connected in series to a bit line and formed in the well;
- a buffer formed in the substrate outside the well and connected to the bit line;
- at least one de-coupling transistor configured to de-couple the buffer from the bit line, the de-coupling transistor being formed in the well;
- at least one pre-charge transistor configured to selectively apply a pre-charge voltage to the bit line, the pre-charge transistor being formed in the well;
- and
- a blocking transistor connected to the de-coupling transistor and formed outside the well, the blocking transistor configured to selectively cut off the buffer from the bit line.
A non-volatile memory device, comprising:
- a first region of a substrate including a plurality of memory cell transistors connected in series to a bit line;
- a second region of the substrate including a buffer connected to the bit line;
- and
- at least one de-coupling transistor configured to de-couple the buffer from the bit line, the de-coupling transistor being formed in the first region;
- at least one well in the substrate defining one of the first and second regions;
- and
- a blocking transistor connected to the de-coupling transistor and formed outside the well, the blocking transistor configured to selectively cut off the buffer from the bit line.
A non-volatile memory device, comprising:
- a first region of a substrate including a plurality of memory cell transistors connected in series to a bit line;
- a second region of the substrate including a buffer connected to the bit line;
- and
- at least one de-coupling transistor configured to de-couple the buffer from the bit line, the de-coupling transistor being formed in the first region;
- at least one pre-charge transistor configured to selectively apply a pre-charge voltage to the bit line, the pre-charge transistor being formed in the first region;
- at least one well in the substrate defining one of the first and second regions;
- and
- a blocking transistor connected to the de-coupling transistor and formed outside the well, the blocking transistor configured to selectively cut off the buffer from the bit line.
Dependencies are inferred from the claim text.