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US 7,733,690 B2Granted
Semiconductor integrated circuit having a latch circuit
AssigneePanasonic Corporation
InventorTomoyuki Kumamaru
Life of this patent
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Abstract
A semiconductor integrated circuit comprising a data holding circuit sets the data holding circuit to a desired data state by first setting the power-supply voltage of the data holding circuit to be less than a specified voltage, and then setting the power-supply voltage of the data holding circuit to the specified voltage or greater, regardless of the data state that is stored beforehand in the data holding circuit.
Claims24
A semiconductor integrated circuit comprising
- a latch circuit;
- wherein:
- the latch circuit comprises a first inverter and a second inverter;
- the first inverter comprises a first NMOS transistor and a first PMOS transistor;
- the second inverter comprises a second NMOS transistor and a second PMOS transistor;
- a relationship of current capability of the first NMOS transistor and the first PMOS transistor is constant when a power-supply voltage becomes less than a specified voltage;
- and
- a relationship of current capability of the second PMOS transistor and the second NMOS transistor is constant when the power-supply voltage becomes less than the specified voltage.
5 more elements
Dependencies are inferred from the claim text.