Asymmetrical SRAM cell with 4 double-gate transistors

A random access memory cell of SRAM type comprising an access transistor having a first gate electrode connected to a word line, a first source/drain electrode connected to a bit line, and a second source/drain electrode connected to a gate electrode of a first load transistor, to a gate electrode of a driver transistor and to a first source/drain electrode of a second load transistor, a second source/drain electrode of the second load transistor being connected to a supply voltage, the first load transistor and the driver transistor being connected in series to the terminals of the supply voltage, wherein

• the access transistor comprises at least one second gate electrode electrically independent from the first gate electrode,
• the second load transistor comprises at least one second gate electrode electrically independent from a first gate electrode of the second load transistor
• the second gate electrode of the access transistor being connected to the first gate electrode of the second load transistor and the second gate electrode of the second load transistor being connected to the supply voltage, and
• the access transistor has a current/voltage characteristic with a drain current depending more greatly on the voltage applied to its first gate than the current/voltage characteristics of the other transistors of the memory cell.