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US 7,733,687 B2Granted
WAK devices in SRAM cells for improving VCCMIN
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsSubramani Kengeri, Bharath Upputuri
Life of this patent
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Abstract
A memory circuit includes a bit line; a word line; a first power supply node having a first power supply voltage; a first power supply line connected to the first power supply node; a second power supply node selected from a group consisting of a floating node and a node having a second power supply voltage lower than the first power supply voltage; a second power supply line configured to switch connections between the first and the second power supply nodes; a write-assist-keeper (WAK) device coupling the first and the second power supply lines; and a static random access memory (SRAM) cell connected to the bit line, the word line and the second power supply line.
Claims27
A memory circuit comprising:
- a bit line;
- a first word line;
- a second word line adjacent the first word line;
- a first power supply node having a first power supply voltage;
- a first power supply line connected to the first power supply node;
- a second power supply node selected from a group consisting of a floating node and a node having a second power supply voltage lower than the first power supply voltage;
- a second power supply line configured to switch connections between the first and the second power supply nodes;
- a write-assist-keeper (WAK) device coupling the first and the second power supply lines;
- an additional WAK device coupled between the first and the second power supply lines;
- a first static random access memory (SRAM) cell connected to the bit line, the first word line, and the second power supply line;
- and
- a second SRAM cell connected to the bit line, the second word line, and the second power supply line.
9 more elements
A memory circuit comprising:
- a static random access memory (SRAM) array comprising:
- a first plurality of power supply lines having a first power supply voltage extending in a column direction;
- a plurality of power supply nodes extending in the column direction, each selected from a group consisting of a floating node and a node having a second power supply voltage, wherein the second power supply voltage is lower than the first power supply voltage;
- a second plurality of power supply lines, each configured to switch connections between one of the first plurality of power supply lines and one of the plurality of power supply nodes;
- a plurality of bit lines extending in the column direction;
- a plurality of word lines extending in a row direction;
- a plurality of SRAM cells, each connected to one of the plurality of bit lines, one of the plurality of word lines, and one of the second plurality of power supply lines;
- and
- a plurality of write-assist-keeper (WAK) devices, each coupled between one of the first plurality of power supply lines and one of the second plurality of power supply lines, wherein two neighboring WAK devices connected to a same one of the second plurality of power supply lines are separated by at least two SRAM cells.
6 more elements
A method of operating a memory circuit, the method comprising:
- providing a static random access memory (SRAM) cell;
- providing a first power supply line having a first power supply voltage;
- providing a second power supply line;
- providing a write-assist-keeper (WAK) device coupled between the first and the second power supply lines, wherein the WAK device is adjacent the SRAM cell;
- providing an additional WAK device coupled between the first and the second power supply lines, wherein the WAK device is further from the SRAM cell than the WAK device;
- performing a read operation comprising:
- connecting the second power supply line to the first power supply voltage;
- and
- reading from the SRAM cell;
- and
- performing a write operation comprising:
- connecting the second power supply line to a power supply node selected from a group consisting of a floating node and a node having a second power supply voltage lower than the first power supply voltage;
- and
- writing into the SRAM cell.
11 more elements
A method of operating a memory circuit, the method comprising:
- providing the memory circuit comprising:
- a plurality of static random access memory (SRAM) cells comprising more than one SRAM cell and arranged as an array with rows and columns;
- a first plurality of power supply lines having a first power supply voltage, each being adjacent to one of the columns;
- a second plurality of power supply lines, each being adjacent to one of the columns and providing power to one of the columns of the array;
- a plurality of write-assist-keeper (WAK) devices, each coupled between one of the first plurality of power supply lines and one of the second plurality of power supply lines, wherein the plurality of WAK devices is substantially evenly distributed throughout the array, and wherein at least two of the plurality of WAK devices are connected to a same one of the columns of the array;
- performing a read operation to one (operation cell) of the plurality of SRAM cells comprising:
- connecting one of the second plurality of power supply lines connected to the operation cell to the first power supply voltage;
- and
- reading from the operation cell;
- and
- performing a write operation comprising:
- connecting the one of the second plurality of power supply lines connected to the operation cell to a power supply node selected from a group consisting of a floating node and a node having a second power supply voltage lower than the first power supply voltage;
- and
- writing into the operation cell.
11 more elements
Dependencies are inferred from the claim text.