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US 7,733,686 B2Granted
Pulse width control for read and write assist for SRAM circuits
AssigneeTexas Instruments Incorporated
InventorMichael Patrick Clinton
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Abstract
An exemplary system and methods implementing pulse width control in SRAM bit cell arrays that vary in size are described.
Claims20
A system comprising:
- a controller that monitors and controls pulse width of control signals for read and write assist for bit cells;
- and
- a memory coupled to the controller, comprised of:
- a static random access memory (SRAM) device that includes the bit cells, and
- a tracking circuit operative for controlling voltage levels of the SRAM device that receives a pulse and introduces a delay to the pulse such that the a final pulse width is based on a length of a bit line connected to the bit cells and the final pulse width is used in controlling voltage levels for the SRAM device.
2 more elements
A static random access memory (SRAM) device comprising:
- a tracking circuit operative for controlling voltage levels of the SRAM device in response to receiving a known pulse, the tracking circuit comprising RC circuits and inverters;
- and
- an array of bit cells that are connected to one or more bit lines, wherein the tracking circuit receives the known pulse and introduces a delay such that a final pulse width for a final pulse is generated based on the delay, and the final pulse width is used in controlling voltage levels for the SRAM device.
A memory device comprising:
- a plurality of bit lines having an associated bit line length;
- a read and write assist circuit positioned along at least one of the plurality of bit lines, the read and write assist circuit comprising:
- an input for receiving a first pulse;
- a first inverter coupled to the input;
- first and second series connected RC pairs, the first series connected RC pair coupled to the first inverter;
- second and third series connected inverters, the second series connected inverter coupled to the second series connected RC pair;
- a NAND gate coupled to the input and the second series connected inverter;
- and
- a fourth inverter coupled to the NAND device,
- wherein the a read and write assist circuit produces a final pulse having a final pulse width associated with a delay in the read and write assist circuit.
7 more elements
Dependencies are inferred from the claim text.