Cross point memory cell with distributed diodes and method of making same
AssigneeSanDisk 3D LLC
InventorsRoy E. Scheuerlein, Luca Fasoli
Life of this patent
Estimating the term…
Abstract
A cross point memory cell includes a portion of a first distributed diode, a portion of a second distributed diode, a memory layer located between the portion of the first distributed diode and the portion of a second distributed diode, a bit line electrically connected to the first distributed diode, and a word line electrically connected to the second distributed diode.
Claims29
A cross point memory cell, comprising:
- a portion of a first distributed diode;
- a portion of a second distributed diode;
- a memory layer located directly between the portion of the first distributed diode and the portion of a second distributed diode;
- a bit line electrically connected to the first distributed diode;
- and
- a word line electrically connected to the second distributed diode.
A memory device comprising a plurality of cross point memory cells, wherein:
- each memory cell of the plurality of memory cells comprises a resistivity switching material located directly between two distributed diodes;
- and
- each one of said two distributed diodes of each memory cell is shared with different memory cells of the plurality of memory cells.
A semiconductor device comprising a plurality of cross point memory cells, wherein each memory cell of the plurality of memory cells comprises:
- a first rail structure, wherein the first rail structure comprises a first distributed diode;
- a second rail structure, wherein the second rail structure comprises a second distributed diode;
- and
- a memory layer located directly between the first and the second rail structures.
A method of manufacturing a semiconductor device, comprising:
- forming a first rail structure, wherein the first rail structure comprises a first distributed diode;
- forming a memory layer directly over the first rail structure;
- and
- forming a second rail structure directly over the first layer of memory material, wherein the second rail structure comprises a second distributed diode.
A memory array, comprising:
- a plurality of bit lines;
- a plurality of word lines;
- a plurality of first distributed diodes;
- a plurality of second distributed diodes;
- and
- a plurality of memory cells;
- wherein:
- each memory cell of the plurality of the memory cells comprises a memory layer located between a portion of one of the plurality of the first distributed diodes and a portion of one of the plurality of the second distributed diodes;
- at least two of the plurality of the first distributed diodes are connected to each one of the plurality of bit lines;
- at least two of plurality of the second distributed diodes are connected to each one of the plurality of word lines;
- each of the plurality of the first distributed diodes is connected to the memory layer of at least two of the plurality of the memory cells;
- and
- each of the plurality of the second distributed diodes is connected to the memory layer of at least two of the plurality of the memory cells.
Dependencies are inferred from the claim text.