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US 7,733,681 B2Granted
Ferroelectric memory with amplification between sub bit-line and main bit-line
OwnerHideaki Miyamotoinventor
Life of this patent
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Abstract
A memory capable of suppressing increase of the chip area thereof while increasing a read voltage is obtained. This memory comprises a memory cell array including a plurality of subarrays, a sub bit line arranged on each subarray and provided to be connectable to a main bit line, a storage portion connected between the word line and the sub bit line and a first transistor having a gate connected to the sub bit line and a first source/drain region connected to the main bit line for controlling the potential of the main bit line on the basis of the potential of the sub bit line in a read operation.
Claims19
A memory comprising:
- a memory cell array including a plurality of subarrays;
- a word line arranged on the memory cell array;
- a main bit line arranged to intersect with the word line;
- a sub bit line arranged on each of the subarrays and configured to be connectable to the main bit line;
- a storage portion connected between the word line and the sub bit line;
- and
- a first transistor having a gate connected to the sub bit line, a first source/drain region connected to the main bit line and configured to control a potential of the main bit line during a read operation based on a potential of the sub bit line, and a second source/drain region configured to be connected to a reference higher than ground fixed voltage to maintain the first transistor in an OFF-state during a write operation to the storage portion.
4 more elements
A memory, comprising:
- a main bit line;
- a sub bit line connectable to the main bit line;
- first terminal means of a first transistor for connecting the first transistor to the main bit line to control, during a read operation, a potential of the main bit line based on a potential of the sub bit line;
- and
- second terminal means of the first transistor for connecting the first transistor to a first voltage higher than ground to maintain, during both high level data and low level data write operations, the first transistor in an OFF-state.
2 more elements
Dependencies are inferred from the claim text.