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US 7,733,661 B2Granted
Chip carrier and fabrication method
AssigneeSTATS ChipPAC, Ltd.
InventorsDean Paul Kossives, Byung Joon Han
Life of this patent
Estimating the term…
Abstract
A substrate having a ground plane, a first side, and a second side is provided. A via that electrically connects the first side to the second side is formed. A printed wire is formed on the first side, and a printed wire is formed on the second side. A passive component is formed on the first side. The passive component is formed free of the ground plane. An active component is attached to the first side.
Claims14
A method for manufacturing a chip carrier, comprising:
- providing a substrate having a ground plane, a first side, and a second side;
- forming a via that electrically connects the first side to the second side;
- forming a printed wire on the first side;
- forming a printed wire on the second side;
- forming a passive component on the first side, the passive component free of the ground plane;
- and
- attaching an active component to the first side, the active component spaced a first distance from the passive component,
- forming a solder ball on the second side;
- and
- forming the solder ball in a region on the second side outside a region located under the passive component.
7 more elements
A method for manufacturing a chip carrier, comprising:
- providing a substrate having a ground plane, a first side, and a second side;
- forming vias that electrically connect the first side to the second side, the vias being coaxial structures;
- forming printed wires on the first side;
- forming printed wires on the second side;
- forming passive components on the first side, the passive components free of the ground plane;
- and
- attaching fabricated active components to the first side with solder bumps, the fabricated active components spaced a first distance from the passive components,
- electrically connecting the passive components to the active components and vias with the printed wires on the first side;
- and electrically connecting the solder bumps with wires spaced at least 500 μm from the passive components.
6 more elements
A chip carrier, comprising:
- a substrate having a ground plane, a first side, and a second side;
- a via that electrically connects the first side to the second side;
- a printed wire on the first side;
- a printed wire on the second side;
- a passive component, free of the ground plane, formed on the first side;
- and
- an active component attached to the first side, the active component spaced a first distance from the passive component, and
- further comprising a solder ball formed on the second side, wherein the solder ball is formed in a region on the second side located outside a region under the passive component.
5 more elements
A chip carrier, comprising:
- a substrate having a ground plane, a first side, and a second side;
- vias that:
- electrically connect the first side to the second side, and
- are coaxial structures to reduce interference;
- printed wires on the first side;
- printed wires on the second side;
- passive components, spaced at least a second distance from the ground plane, formed on the first side;
- fabricated active components, the fabricated active components spaced a first distance from the passive components;
- and
- solder bumps attaching the fabricated active components to the first sides,
- wherein the printed wires on the first side electrically connect the passive components, the active components, and the vias, and
- further comprising wires, spaced at least 500 μm from the passive components, electrically connecting the solder bumps.
9 more elements
Dependencies are inferred from the claim text.