Repetitive feed-forward algorithm for self-servo-write PLL
AssigneeMarvell International Ltd.
InventorEdward Ying
Life of this patent
Estimating the term…
Loading patent…
AssigneeMarvell International Ltd.
InventorEdward Ying
Estimating the term…
A phase error reduction system includes a control module, a phase-locked loop (PLL) module, and a harmonic removal module. The control module generates source timestamps for a plurality of synchronization marks in a source signal using a clock and generates a plurality of target tirnestamps. The PLL module determines phase errors between the source timestamps and the target timestamps and minimizes the phase errors. The harmonic removal module removes harmonics of the phase errors using a weighted moving average filter (MAF). The harmonic removal module comprises a repetitive feed forward (RFF) module that includes an amplifier the scales the phase errors, a delay buffer that generates RFF commands to reduce the phase errors, and a summing module. The MAF filters the RFF commands. The summing module provides sums of the phase errors scaled by the amplifier and the RFF commands filtered by the weighted MAF to the delay buffer.
A phase error reduction system, comprising:
A phase error reduction method, comprising:
A phase error reduction system, comprising:
Dependencies are inferred from the claim text.