US 7,733,182 B2 · Hybrid class AB super follower

Abstract

Various embodiments of a hybrid class AB super follower circuit are provided. One embodiment is a follower circuit comprising: an input node for receiving an input voltage signal; an output node for driving a capacitive load based on the input voltage signal; a transistor M1 having a gate terminal connected to the input node for receiving the input voltage signal, a source terminal connected to the output node, and a drain terminal; a feedback loop comprising a second transistor M2, a third transistor M3 and a fourth transistor M4, wherein: the gate and source terminals of the second transistor M2 are connected to a current source I2, and the drain terminal of the second transistor M2 is connected to the output node; the source terminal of the third transistor M3 is connected to the current source I2 and the drain terminal of the third transistor M3 is connected to a current source I0; the gate terminal of the fourth transistor M4 is connected to the drain terminal of the third transistor M3, the drain terminal of the fourth transistor M4 is connected to the output node, and the source terminal of the fourth transistor M4 is connected to a ground; and a replica bias circuit for providing a voltage bias signal to the gate terminal of the third transistor.

Claims4

Dependent claims

A follower circuit comprising:

an input node for receiving an input voltage signal;
an output node for driving a capacitive load based on the input voltage signal;
a transistor M1 having a gate terminal connected to the input node for receiving the input voltage signal, a source terminal connected to the output node, and a drain terminal;
a feedback loop comprising a second transistor M2, a third transistor M3 and a fourth transistor M4, wherein:
the gate and source terminals of the second transistor M2 are connected to a current source I2, and the drain terminal of the second transistor M2 is connected to the output node;
the source terminal of the third transistor M3 is connected to the current source I2 and the drain terminal of the third transistor M3 is connected to a current source I0;
the gate terminal of the fourth transistor M4 is connected to the drain terminal of the third transistor M3, the drain terminal of the fourth transistor M4 is connected to the output node, and the source terminal of the fourth transistor M4 is connected to a ground;
and
a replica bias circuit for providing a voltage bias signal to the gate terminal of the third transistor.

6 more elements

Dependencies are inferred from the claim text.

Hybrid class AB super follower

Life of this patent

Hybrid class AB super follower

Life of this patent

Abstract

Claims4