Amplifier for driving external capacitive loads

An apparatus having a zero-pole that is dependant on an ESR and a load, the apparatus comprising:

• an amplifier stage that receives a first input voltage and a bias voltage, wherein the amplifier stage includes:
• a first current source coupled to the bias voltage;
• a first FET coupled at its drain to the first current source;
• a second FET coupled at its drain to the first current source;
• a second current source coupled to the bias voltage;
• a third FET coupled to the second current source at its drain and to the source of the first transistor at its gate;
• a fourth FET coupled to the second current source at its drain and to the source of the second transistor at its gate;
• a current mirror coupled to the bias voltage;
• and
• a transistor coupled to the current mirror at an output node and coupled to the source of the fourth FET at an internal node;
• an intermediate stage that is coupled to the output node of the amplifier stage, wherein the intermediate stage outputs an intermediate voltage to an intermediate node;
• a first capacitor coupled between at least one of the internal transistors at an internal node and the intermediate node;
• a power transistor coupled between a second input voltage and the intermediate node;
• a second capacitor coupled between the internal node and the power transistor, wherein the second capacitor provides a third input voltage to the power transistor, wherein the ratio of the capacitance of the first capacitor to the capacitance of the second capacitor controls the position of the zero-pole;
• and
• a feedback stage coupled to the intermediate node and to the amplifier stage, wherein the feedback stage is adapted to output an output voltage to a load, and wherein the feedback stage provides a feedback voltage to the gate of the first FET.

An apparatus having a zero-pole that is dependant on an ESR and a load, the apparatus comprising:

• an amplifier stage that receives a first input voltage and a bias voltage, wherein the amplifier stage includes:
• a first current source coupled to the bias voltage;
• a first FET coupled at its drain to the first current source;
• a second FET coupled at its drain to the first current source;
• a second current source coupled to the bias voltage;
• a third FET coupled to the second current source at its drain and to the source of the first transistor at its gate;
• a fourth FET coupled to the second current source at its drain and to the source of the second transistor at its gate;
• a current mirror coupled to the bias voltage;
• a transistor coupled to the current mirror at an output node and coupled to the source of the fourth FET at an internal node;
• a fifth FET coupled to the source of the third FET at its drain;
• and
• a sixth FET coupled to internal node at its drain, wherein the gate of the fifth FET is coupled to the gate of the sixth FET;
• an intermediate stage that is coupled to the output node of the amplifier stage, wherein the intermediate stage outputs an intermediate voltage to an intermediate node;
• a first capacitor coupled between at least one of the internal transistors at an internal node and the intermediate node;
• a power transistor coupled between a second input voltage and the intermediate node;
• a second capacitor coupled between the internal node and the power transistor, wherein the second capacitor provides a third input voltage to the power transistor, wherein the ratio of the capacitance of the first capacitor to the capacitance of the second capacitor controls the position of the zero-pole;
• and
• a feedback stage coupled to the intermediate node and to the amplifier stage, wherein the feedback stage is adapted to output an output voltage to a load, and wherein the feedback stage includes:
• and
• a feedback node coupled to the gate of the first FET;
• an impedance coupled between the intermediate node and the output node;
• a voltage divider coupled to the output node to the feedback node;
• a third capacitor coupled between the intermediate node and the feedback node;
• and
• a fourth capacitor coupled between the output node and the feedback node.