Combination trim and CMFB circuit and method for differential amplifiers

A method for providing input offset correction and common mode feedback in a differential amplifier, the method comprising:

• (a) providing an input stage including first and second input transistors and first and second load devices, each of the first and second input transistors including a control electrode and first and second electrodes, the first electrodes of the first and second input transistors being connected together, the second electrode of the first input transistor being coupled by a first conductor to a terminal of the first load device, the second electrode of the second input transistor being coupled by a second conductor to a terminal of the second load device;
• and
• (b) combining CMFB (common mode feedback) circuitry including first, second, and third transistors with offset correction circuitry including the second transistor and the third transistor and an offset generator circuit, each of the first, second, and third transistors having a control electrode and first and second electrodes, by
• (1) coupling the first electrodes of the first, second, and third transistors to a third conductor that is coupled to a first tail current source, coupling the second electrodes of the second and third transistors to the first and second conductors, respectively,
• (2) applying a common mode output reference voltage to the control electrode of the first transistor, and
• (3) applying first and second trim voltages to the control electrodes of the third and second transistors, respectively.

Circuitry for providing input offset correction and common mode feedback in a differential amplifier, the circuitry comprising:

• (a) an input stage including first and second input transistors and first and second load devices, each of the first and second input transistors including a control electrode and first and second electrodes, the first electrodes of the first and second input transistors being connected together, the second electrode of the first input transistor being coupled by a first conductor to a terminal of the first load device, the second electrode of the second input transistor being coupled by a second conductor to a terminal of the second load device;
• and
• (b) means for combining CMFB (common mode feedback) circuitry including first, second, and third transistors with offset correction circuitry including the second transistor and the third transistor and an offset generator circuit, each of the first, second, and third transistors having a control electrode and first and second electrodes, including
• (1) means for coupling the first electrodes of the first, second, and third transistors to a third conductor that is coupled to a tail current source, and means for coupling the second electrodes of the second and third transistors to the first and second conductors, respectively,
• (2) means for applying a common mode output reference voltage to the control electrode of the first transistor, and
• (3) means for applying first and second trim voltages to the control electrodes of the third and second transistors, respectively.