US 7,733,168 B2Granted

Fully differential comparator and fully differential amplifier

AssigneePanasonic Corporation

InventorMasahiro Higuchi

Life of this patent

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Abstract

A first to a fourth sampling switch (1a to 1d), a first to a fourth sampling capacitance (4 to 7), and a first and a second charge redistribution switch (2a, 2b) are provided on the input side of a differential amplifier (8). A first and a second reset switch (3a, 3b) are provided between inputs and outputs of the differential amplifier (8). A positive-polarity input signal voltage (Vinp), a negative-polarity comparison reference voltage (Vrefn), a positive-polarity comparison reference voltage (Vrefp), and a negative-polarity input signal voltage (Vinn) are applied via the first to fourth sampling switches (1a to 1d) to one ends of the first to fourth sampling capacitances (4 to 7), respectively. During a reset period, the reset of the differential amplifier (8) is released after sampling of the voltages. During a comparison period, the first and second charge redistribution switches (2a, 2b) are caused to be in a conduction state.

Claims12

Dependent claims

A fully differential comparator comprising:

a first to a fourth sampling switch which receive a switch control signal indicating a reset period and a comparison period and are in a conduction state during the reset period, wherein the reset period and the comparison period do not overlap each other;
a first to a fourth sampling capacitance to one ends of which a first to a fourth input voltage are separately applied via the first to fourth sampling switches, respectively, during the reset period;
a differential amplifier having a first input terminal to which the other ends of any two of the first to fourth sampling capacitances are connected in common, and a second input terminal to which the other ends of the other two sampling capacitances are connected in common;
a first charge redistribution switch which causes, during the comparison period, one end connected to any of the first to fourth sampling switches of one of the two sampling capacitances connected to the first input terminal and one end connected to any of the first to fourth sampling switches of one of the two sampling capacitances connected to the second input terminal, to be in a conduction state;
and
a second charge redistribution switch which causes, during the comparison period, one end connected to any of the first to fourth sampling switches of the other of the two sampling capacitances connected to the first input terminal and one end connected to any of the first to fourth sampling switches of the other of the two sampling capacitances connected to the second input terminal, to be in a conduction state,
wherein the differential amplifier outputs, during the comparison period, a first output signal and a second output signal, depending on a difference between a voltage level of the first input terminal of the differential amplifier and a voltage level of the second input terminal of the differential amplifier.

4 more elements

A fully differential amplifier circuit comprising:

a first to a fourth sampling switch which receive a switch control signal indicating a reset period and an amplification period and are in a conduction state during the reset period, wherein the reset period and the amplification period do not overlap each other;
a first to a fourth sampling capacitance to one ends of which a first to a fourth input voltage are applied via the first to fourth sampling switches, respectively, during the reset period;
a differential amplifier having a first input terminal to which the other ends of any two sampling capacitances of the first to fourth sampling capacitances are connected in common, and a second input terminal to which the other ends of the other two sampling capacitances are connected in common;
a first charge redistribution switch which causes, during the amplification period, one end connected to any of the first to fourth sampling switches of one of the two sampling capacitances connected to the first input terminal and one end connected to any of the first to fourth sampling switches of one of the two sampling capacitances connected to the second input terminal, to be in a conduction state;
a second charge redistribution switch which causes, during the amplification period, one end connected to any of the first to fourth sampling switches of the other of the two sampling capacitances connected to the first input terminal and one end connected to any of the first to fourth sampling switches of the other of the two sampling capacitances connected to the second input terminal, to be in a conduction state;
a first feedback capacitance having a first terminal connected to the first input terminal of the differential amplifier and a second terminal connected to a first output terminal of the differential amplifier;
and
a second feedback capacitance having a first terminal connected to the second input terminal of the differential amplifier and a second terminal connected to a second output terminal of the differential amplifier,
wherein, during the amplification period, the differential amplifier outputs a first output signal to the first output terminal of the differential amplifier and a second output signal to the second output terminal of the differential amplifier, depending on a difference between a voltage level of the first input terminal of the differential amplifier and a voltage level of the second input terminal of the differential amplifier.

6 more elements

Dependencies are inferred from the claim text.

Facts

Application: 12/092,675Filed 31 Aug 2006
Priority: JP 2005-33541521 Nov 2005
Published: US 2009/0179699 A116 Jul 2009
Granted: 8 Jun 2010
Term ends: Not estimatedThe source records don’t support an estimate.

Classification11 codes

H03M 1/1245
Sampling or signal conditioning arrangements specially adapted for A/D converters: details of sampling arrangements or methods
H03F 3/005
Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements: using switched capacitors, e.g. dynamic amplifiers;…
H03F 3/45475
Characterised by the way of implementation of the active amplifying circuit in the differential amplifier: using IC blocks as the active…
H03F 3/45968
Using IC blocks as the active amplifying circuit: by offset reduction