System and method for common mode bias for high frequency buffers
AssigneeBroadcom Corporation
InventorJohn Leete
Life of this patent
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Abstract
Methods and systems for reducing parasitic capacitance of a buffer for an electric circuit are disclosed and may include coupling a gate of a first transistor to a first differential input of the buffer via a first capacitor, coupling a gate of a second transistor to a second differential input of the buffer via a second capacitor. The first and second transistors may be biased by a common mode output of a direct current (DC) voltage source for the buffer. The common mode output of the DC voltage source may be directly coupled to at least one differential output of the buffer via an inductor. The first transistor and the second transistor may comprise NMOS transistors and/or PMOS transistors. The DC voltage source may comprise a PMOS transistor and/or an NMOS transistor.
Claims32
A method for reducing parasitic capacitance of a buffer for an electric circuit, the method comprising:
- coupling a gate of a first transistor to a first differential input of the buffer via a first capacitor;
- coupling a gate of a second transistor to a second differential input of the buffer via a second capacitor;
- common mode self-biasing said first transistor via a first inductor, a first resistor, and a common mode output of a direct current (DC) voltage source that is directly coupled to said first inductor and said first resistor;
- and
- common mode self-biasing said second transistor via a second inductor, a second resistor, and said common mode output of said DC voltage source that is directly coupled to said second inductor and said second resistor.
A circuit for reducing parasitic capacitance of a buffer for an electric circuit, the circuit comprising:
- a first transistor, wherein a gate of said first transistor is coupled to a first differential input of the buffer via a first capacitor;
- a second transistor, wherein a gate of said second transistor is coupled to a second differential input of the buffer via a second capacitor;
- and
- a direct current (DC) voltage source, wherein said first transistor is common mode self-biased via a first inductor, a first resistor, and a common mode output of said DC voltage source that is directly coupled to said first inductor and said first resistor, and wherein said second transistor is common mode self-biased via a second inductor, a second resistor, and said common mode output of said DC voltage source that is directly coupled to said second inductor and said second resistor.
Dependencies are inferred from the claim text.