US 7,733,157 B2Granted

Noise-reducing transistor arrangement

AssigneeInfineon Technologies AG

InventorsRalf Brederlow, Jeongwook Koh, Christian Pacha, Roland Thewes

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Abstract

Noise-reducing transistor arrangement having first and second field effect transistors (FETs) having source terminals coupled together, drain terminals coupled together, and control terminals for application of a first or second signal. A clock generator unit is configured to provide the first and second signals alternately to the FETs with an alternating frequency which is at least as great as the cut-off frequency of the noise characteristic of the FETs, or with a reciprocal alternating frequency which is less than a mean lifetime of an occupation state of a defect in the boundary region between channel region and gate insulating layer of the FETs. The first signal is applied to the control terminal of the first FET and, simultaneously, the second signal to the control terminal of the second FET. The second signal is applied to the control terminal of the first FET and, simultaneously, the first signal to the control terminal of the second FET.

Claims31

Dependent claims

A noise-reducing transistor arrangement, comprising:

a first and a second field effect transistor, each of which has a source terminal, a drain terminal, and a control terminal for application of a first signal or a second signal;
wherein the source terminal of the first field effect transistor and the source terminal of the second field effect transistor are coupled to one another, and
wherein the drain terminal of the first field effect transistor and the drain terminal of the second field effect transistor are coupled to one another, and
a clock generator unit being configured to generate a first clock signal and a second clock signal, wherein the control terminal of the first field effect transistor is coupled to a first switching element which is switched by means of the first clock signal, and the control terminal of the second field effect transistor is coupled to a second switching element, which is switched by means of the second clock signal, wherein the first and the second switch elements are configured to switch between a connection with the first signal and a connection with the second signal such that the first signal and the second signal are alternately provided to the field effect transistors with an alternating frequency which is at least as great as the cut-off frequency of the noise characteristic of the field effect transistors, or with a reciprocal alternating frequency which is less than a mean lifetime of an occupation state of a defect in the boundary region between channel region and gate insulating layer of the field effect transistors,
wherein the first clock signal and the second clock signal are configured to control the first switch element and the second switch element respectively such that
the first signal is applied to the control terminal of the first field effect transistor and, simultaneously, the second signal is applied to the control terminal of the second field effect transistor, and
the second signal is applied to the control terminal of the first field effect transistor and, simultaneously, the first signal is applied to the control terminal of the second field effect transistor.

4 more elements

A method of reducing the noise of field effect transistors, comprising:

connecting a first field effect transistor and a second field effect transistor to one another, each of the field effect transistors having a source terminal and a drain terminal and also a control terminal for application of a first or a second signal, wherein the source terminal of the first field effect transistor and the source terminal of the second field effect transistor are coupled to one another, and wherein the drain terminal of the first field effect transistor and the drain terminal of the second field effect transistor are coupled to one another;
and
applying the first signal and the second signal alternately to the field effect transistors with an alternating frequency which is at least as great as the cut-off frequency of the noise characteristic of the field effect transistors, or with a reciprocal alternating frequency which is less than a mean lifetime of an occupation state of a defect in the boundary region between channel region and gate insulating layer of the field effect transistors, wherein the applying step comprises:
applying the first signal to the control terminal of the first field effect transistor and, simultaneously applying the second signal to the control terminal of the second field effect transistor;
and
applying the second signal to the control terminal of the first field effect transistor and, simultaneously applying the first signal to the control terminal of the second field effect transistor.

3 more elements

Dependencies are inferred from the claim text.