High speed level shifter
AssigneeInfineon Technologies AG
InventorsMarco Flaibani, Emanuele Bodano, Cristian Garbossa
Life of this patent
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Abstract
The invention relates to a level shifter comprising an input stage having a parasitic capacitance and a first input terminal for applying an input signal, a limiter stage having a second input terminal for applying a switching signal, wherein said input stage is coupled between a first supply terminal and said limiter stage, an output stage being coupled between a second supply terminal and said limiter stage and providing an output signal which is a level shifted version of said input signal, and a current source being adapted for injecting a current pulse into said parasitic capacitance dependent on variations of said switching signal over time.
Claims21
A level shifter comprising:
- an input stage having a parasitic capacitance and a first input terminal for receiving an input signal;
- a limiter stage having a second input terminal for receiving a switching signal, wherein said input stage is coupled between a first supply terminal and said limiter stage;
- an output stage being coupled between a second supply terminal and said limiter stage, the output stage providing an output signal that is a level shifted version of said input signal;
- and
- a current source adapted to inject a current pulse into said parasitic capacitance dependent on variations of said switching signal over time.
A semiconductor arrangement comprising
- a semiconductor switch;
- a floating driver circuit coupled to a control terminal of said semiconductor switch for controlling a potential of said control terminal;
- and
- a level shifter coupled between a first input terminal for applying an input signal and said floating driver circuit, the level shifter comprising:
- an input stage having a parasitic capacitance and a first input terminal for receiving an input signal;
- a limiter stage having a second input terminal for receiving a switching signal, wherein said input stage is coupled between a first supply terminal and said limiter stage;
- an output stage being coupled between a second supply terminal and said limiter stage, the output stage providing an output signal that is a level shifted version of said input signal, the output signal being coupled to an input of the floating driver circuit;
- and
- a current source adapted to inject a current pulse into said parasitic capacitance dependent on variations of said switching signal over time.
A circuit comprising:
- a first transistor with a control terminal coupled to an input node, the first transistor having a current path between a first supply terminal and a first circuit node;
- a second transistor with a control terminal coupled to an inverted input node, the second transistor having a current path between the first supply terminal and a second circuit node;
- a third transistor with a control terminal coupled to a switching signal node, the third transistor having a current path between the first circuit node and a third circuit node;
- a fourth transistor with a control terminal coupled to the control terminal of the third transistor, the fourth transistor having a current path between the second circuit node and a fourth circuit node;
- a fifth transistor with a control terminal coupled to the fourth circuit node, the fifth transistor having a current path between the third circuit node and a bootstrap supply potential node;
- a sixth transistor with a control terminal coupled to the third circuit node, the sixth transistor having a current path between the fourth circuit node and the bootstrap supply potential node;
- and
- a current source coupled between the second circuit node and the bootstrap supply potential node to inject a current into a parasitic capacitance coupled to the second circuit node, the current being dependent on variations of a signal coupled to the signal switching node.
Dependencies are inferred from the claim text.