Operating clock generation system and method for audio applications
AssigneeTexas Instruments Incorporated
InventorsShawn Xianggang Yu, Terry L. Sculley
Life of this patent
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Abstract
A clock signal generator (1) includes a phase locked loop (PLL) circuit (25) which requires a reference clock signal of at least a predetermined first frequency (fDIGCLK). A first clock signal (REFCLK) of a second frequency (fREF) that is substantially lower than the first frequency (fDIGCLK) is multiplied so as to produce a second clock signal (DIGCLK) which has a frequency at least as high as the first frequency (fDIGCLK) and which is phase-locked with respect to the first clock signal (REFCLK). The second clock signal (DIGCLK) is applied to a reference signal input of the PLL circuit (25), which produces an output clock signal (PLLCLK or CLKOUT).
Claims20
A clock signal generating system for generating an output clock signal comprising:
- a phase locked loop (PLL) circuit which requires a reference clock signal of at least a predetermined first frequency, an output of the PLL circuit being coupled to generate the output clock signal;
- and
- a clock signal multiplication circuit having:
- an oscillator;
- a counter circuit that is clocked by an oscillator clock signal produced by the oscillator and that is coupled to receive a first clock signal of a second frequency that is substantially lower than the first frequency, wherein the counter circuit samples its contents in response to the first clock signal;
- a clock filter and clock period estimator circuit that is coupled to receive the sampled contents of the counter circuit;
- a first delta-sigma modulator that is coupled to receive an estimate which is representative of the period of the first clock signal multiplied by a ratio of the first frequency to the second frequency, and which is produced by the clock filter and clock period estimator circuit for producing an integer representation of the estimate;
- a memory for receiving a predetermined number of the integer representations;
- and
- a first divider circuit coupled to divide the oscillator clock signal by the predetermined number of the integer representations to generate a second clock signal which has a frequency at least as high as the first frequency, wherein the output clock signal is phase-locked with respect to the first clock signal, and wherein a reference clock input of the PLL circuit is coupled to receive the second clock signal.
An apparatus comprising:
- a clock signal multiplication circuit having:
- an oscillator that generates an oscillator signal;
- a counter circuit that is clocked by the oscillator signal and that receives a reference clock signal;
- a filter and estimator circuit that is coupled to the counter circuit;
- a delta-sigma modulator that is coupled to the filter and estimator circuit, wherein the delta-sigma modulator produces a plurality of integer representations of an estimate of the period of the reference clock signal multiplied by a ratio of the frequency of the reference clock signal to a predetermined frequency;
- a memory that is coupled to the delta-sigma modulator that stores the integer representations;
- and
- a divider that divides the oscillator signal by the integer representations;
- and
- a PLL having a reference input that is coupled to the divider, wherein the predetermined frequency is a lower threshold frequency for the operation of the PLL.
A method comprising:
- producing an estimate that is representative of a period of a first clock signal multiplied by a ratio of a predetermined frequency to a frequency of the first clock signal;
- producing a plurality of integer representations of the estimate with a sigma-delta modulator;
- storing the integer representations in a memory;
- dividing an oscillator clock signal by each integer representation from the memory to generate a pulse which lasts during a number of cycles of the oscillator clock signal equal to the value of that integer representation so as to generate the second clock signal;
- receiving the second clock signal at a reference clock input of a PLL, wherein the predetermined frequency is a lower threshold frequency for the operation of the PLL;
- and
- generating an output clock signal with the PLL, wherein the output clock signal is phase-locked with respect to the first clock signal.
Dependencies are inferred from the claim text.