Method and apparatus for adaptive clock phase control for LSI power reduction
AssigneeSony Computer Entertainment Inc.
InventorChiaki Takano
Life of this patent
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Abstract
Methods and apparatus for distributing a clock signal to a digital circuit provide for: producing a clock signal; and delaying, advanced, or leaving the clock signal unchanged to produce an output clock signal as a function of a control signal, wherein an amount of delay or advancement between the clock signal and the output clock signal (phase difference) is a function of time variant changes in a magnitude of a power supply voltage to the digital circuit.
Claims11
A clock distribution circuit, comprising:
- a clock source that operates to produce a clock signal;
- a phase adjustment circuit that operates to receive the clock signal and produce a delayed, advanced, or unchanged output clock signal as a function of a control signal, and which operates to vary the phase difference between the clock signal and the output clock in a way that adheres to the following equation:
- φ
-
- (
- t
- )
- =
- -
- β
- T
- 0
-
- ∫
- (
- v
-
- (
- t
- )
- -
- v
- 0
- )
-
-
- ⅆ
- t
- where φ(t) is the phase difference in radians as a function of time variant changes in a magnitude of the power supply voltage v(t), T0 is a cycle time of the clock signal and β is a constrained constant;
- and
- a clock distribution tree that operates to distribute the output clock signal to a plurality of areas of a digital circuit,
- wherein the phase adjustment circuit is that operates to vary an amount of delay or advancement between the clock signal and the output clock signal (phase difference) as a function of time variant changes in a magnitude of a power supply voltage to the digital circuit.
A phase adjustment circuit that operates to receive a clock signal for distribution in an digital circuit and produce a delayed, advanced, or unchanged output clock signal as a function of a control signal, wherein the phase adjustment circuit operates to vary an amount of delay or advancement between the clock signal and the output clock signal as a function of time variant changes in a magnitude of a power supply voltage to the digital circuit, wherein the phase adjustment circuit is operable to vary the phase difference between the clock signal and the output clock as expressed by the following equation:
- φ
-
- (
- t
- )
- =
- -
- β
- T
- 0
-
- ∫
- (
- v
-
- (
- t
- )
- -
- v
- 0
- )
-
- ⅆ
- t
- ,
- wherein φ(t) is the phase difference in radians as a function of time variant changes in a magnitude of the power supply voltage v(t), T0 is a cycle time of the clock signal and β is a constrained constant.
A method of distributing a clock signal to a digital circuit, comprising:
- producing a clock signal;
- and
- delaying, advanced, or leaving the clock signal unchanged to produce an output clock signal as a function of a control signal, wherein an amount of delay or advancement between the clock signal and the output clock signal (phase difference) is a function of time variant changes in a magnitude of a power supply voltage to the digital circuit, the phase difference between the clock signal and the output clock being expressed by the following equation:
- φ
-
- (
- t
- )
- =
- -
- β
- T
- 0
-
- ∫
- (
- v
-
- (
- t
- )
- -
- v
- 0
- )
-
- ⅆ
- t
- ,
- wherein φ(t) is the phase difference in radians as a function of time variant changes in a magnitude of the power supply voltage v(t), T0 is a cycle time of the clock signal and β is a constrained constant.
Dependencies are inferred from the claim text.