SET and SEGR resistant delay cell and delay line for Power-On Reset circuit applications
AssigneeAeroflex Colorado Springs Inc.
InventorMatthew Von Thun
Life of this patent
Estimating the term…
Abstract
A delay line appropriate for use in a POR circuit or other integrated circuit in a space environment combines three separate circuit techniques to improve performance without unnecessarily increasing circuit area or adding to manufacturing costs when compared to a simple inverter delay line. The delay line of the present invention uses the selective placement of capacitors throughout the delay line, one-sided current starving, and the incorporation of one-sided Schmitt trigger circuits. Performance of the delay line is substantially immune to SEGR events (“Single Event Gate Rupture”) and SET events (“Single Event Transients”). Spurious signals produced by SEGR and SET events are quickly and substantially attenuated.
Claims26
An SET and SEGR resistant delay cell configured to be substantially immune to radiation effects, comprising:
- a delay input and a delay output;
- a one-sided current starved input section having an input coupled to the delay input, and an output;
- a capacitor coupled between the output of the input section and ground, wherein the capacitor remains at a substantially zero potential during normal operation and the capacitor is discharged during the normal operation and is only charged when a pulse is passing through the SEGR resistant delay cell;
- and
- a half-Schmitt trigger circuit having an input coupled to the output of the input section, and an output coupled to the delay output.
An SET and SEGR resistant delay line configured to be substantially immune to radiation effects, comprising a plurality of serially-coupled delay cells, each delay cell comprising:
- a delay input and a delay output;
- a one-sided current starved input section having an input coupled to the delay input, and an output;
- a capacitor coupled between the output of the input section and ground, wherein the capacitor remains at a substantially zero potential during normal operation and the capacitor is discharged during the normal operation and is only charged when a pulse is passing through the SEGR resistant delay cell;
- and
- a half-Schmitt trigger circuit having an input coupled to the output of the input section, and an output coupled to the delay output.
A method of operating an SET and SEGR resistant delay cell configured to be substantially immune to radiation effects, comprising the steps of:
- providing a delay input and a delay output;
- providing a one-sided current starved input section having an input coupled to the delay input, and an output;
- providing a capacitor coupled between the output of the input section and ground;
- providing a half-Schmitt trigger circuit having an input coupled to the output of the input section, and an output coupled to the delay output;
- discharging the capacitor during the normal operation such that the capacitor remains at a substantially zero potential during the normal operation;
- and
- charging the capacitor when a pulse passes through the SEGR resistant delay cell.
Dependencies are inferred from the claim text.