Radiation hardened CMOS master latch with redundant clock input circuits and design structure therefor

A radiation hardened master latch comprising:

• a first master latch half circuit;
• and
• a second master latch half circuit identical to and interconnected with the first master latch half circuit,
• wherein
• each of the first and second master latch half circuits has a clock input,
• each of the first and second master latch half circuits includes a clock input circuit in which the clock input is coupled to a plurality of sub-clock nodes,
• the clock input circuit is configured such that the operation of the master latch half circuit is immune to a single upset event affecting at most one of the plurality sub-clock nodes, each of the first and second master latch half circuits has, in addition to the clock input, first and second data inputs, first and second complementary data inputs, a feedback input, a complementary feedback input, a data output, and a complementary data output, the respective clock inputs of the first and second master latch half circuits are connected together in parallel, the respective first and second data inputs and first and second complementary data inputs of the first and second master latch half circuits are connected together in parallel, the data output and the complementary data output of the first master latch half circuit are connected respectively to the feedback input and the complementary feedback input of the second master latch half circuit, and the data output and the complementary data output of the second master latch half circuit are connected respectively to the feedback input and the complementary feedback input of the first master latch half circuit.