Duty cycle correction circuit for high-speed clock signals

A method for correcting duty cycle distortion in high speed clock signals, the method comprising:

• delaying each of first and second differential initial clock signals;
• generating, using a latch, a single-ended output clock signal based on the delayed first and second differential initial clock signals;
• converting the single-ended output clock signal into first and second differential feedback signals;
• and
• adjusting, the delaying, of one or more delay cells, based on the first and second differential feedback signals.

An apparatus for correcting duty cycle distortion in high speed clock signals, the apparatus comprising:

• a first differential buffer that converts an input clock signal into first and second differential initial clock signals;
• a first delay cell that delays the first differential initial clock signals;
• a second delay cell that delays the second differential initial clock signals;
• a latch that generates an output clock signal based on the delayed first and second differential initial clock signals;
• a differential feedback buffer that converts the output clock signal into first and second differential feedback signals;
• a filter that converts the first and second differential feedback signals into first and second direct current (DC) feedback signals, respectively;
• and
• a differential amplifier that generates first and second DC error signals based on the first and second DC feedback signals, wherein the first and second delay cells are adjusted based on the first and second DC error signals.