Delay locked loop circuit and method for eliminating jitter and offset therein

A delay locked loop circuit, comprising:

• a phase-frequency detector outputting a difference signal by detecting a phase difference between an input clock signal and a feedback clock signal;
• a first flip-flop for delaying the difference signal output from the phase-frequency detector to output a first delay signal;
• a second flip-flop for delaying the first delay signal output from the first flip-flop to output a second delay signal;
• an XNOR gate receiving the difference signal, the first delay signal and the second delay signal to output a logic signal;
• a charge pump for generating a control voltage in accordance with the logic signal output from the XNOR gate;
• a bias generator for generating a bias voltage in accordance with the control voltage generated by the charge pump;
• and
• a voltage-controlled element controlled with the bias voltage generated by the bias generator to generate an output clock signal and to output the feedback clock signal to the phase-frequency detector in accordance with the input clock signal.

A method for eliminating jitter and offset between an input clock signal and an output clock signal in a delay locked loop circuit, comprising the steps of:

• determining a phase difference between the input clock signal and a feedback clock signal;
• generating a difference signal corresponding to the phase difference;
• sampling the difference signal to output a sampled signal having a lower frequency than a frequency of the difference signal in accordance with the input clock signal, wherein the step of sampling the difference signal comprises the steps of:
• delaying the difference signal in accordance with the input clock signal to output a first delay signal,
• delaying the first delay signal in accordance with the input clock signal to output a second delay signal, and
• performing XNOR operation of the difference signal, the first delay signal and the second delay signal to output a logic signal as the sampled signal;
• generating a control voltage in accordance with the sampled signal;
• generating a bias voltage corresponding to the control voltage;
• and
• delaying the input clock signal in accordance with the bias voltage to generate the output clock signal and the feedback clock signal, wherein the output clock signal has a phase substantially equal to the input clock signal.