False lock detection mechanism for use in a delay locked loop circuit

A delay locked loop circuit comprising:

• a charge pump circuit configured to charge in response to an assertion of an up signal and to discharge in response to an assertion of a down signal;
• a delay circuit configured to provide a plurality of delayed clock signals and an additional delayed clock signal, each corresponding to a delayed version of a first clock signal;
• a detection circuit coupled to the delay circuit and configured to assert the up signal indicating an occurrence of a transition of the first clock signal and to assert the down signal indicating an occurrence of a transition of a particular delayed clock signal of the plurality of delayed clock signals;
• and
• a false lock circuit configured to provide a reset signal to reset the detection circuit in response to detecting an occurrence of more than a predetermined number of successive clock edges associated with the delayed clock signals within a given clock cycle of the first clock signal, and in response to detecting an occurrence of less than the predetermined number of successive clock edges associated with the delayed clock signals within a given clock cycle of the first clock signal.