High side boosted gate drive circuit
AssigneeTexas Instruments Incorporated
InventorsParas M. Dagli, David John Baldwin, Adam Shook
Life of this patent
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Abstract
A high-side boosted gate drive circuit is disclosed. In a particular example, an output driver is described, comprising a switching device configured to selectively conduct current in response to a charge being present at a control terminal for a duty cycle, a charging device configured to deliver charge to the control terminal based on the first duty cycle, a charge control device configured to selectively couple the charging device to deliver charge to the control terminal and to selectively decouple the charging device from the control terminal to charge the charging device, and a discharge control device configured to remove charge from the control terminal.
Claims16
An apparatus comprising:
- a switching device configured to selectively conduct current in response to a charge being present at a control terminal for a duty cycle;
- a charging device configured to deliver charge to the control terminal based on a first duty cycle;
- a charge control device configured to selectively couple the charging device to deliver charge to the control terminal and to selectively decouple the charging device from the control terminal to charge the charging device, wherein the charge control device includes a field-effect transistor (FET) and blocking diodes, configured to selectively couple the charging device to the control terminal based on a gate voltage and a backgate voltage;
- and
- a discharge control device configured to remove charge from the control terminal.
A circuit comprising:
- a switching device having an n-channel FET, configured to selectively conduct current in response to a charge being present at a gate terminal for an input duty cycle;
- a charging device having a bootstrap capacitor, configured to deliver charge to the gate terminal and to be charged for a second duty cycle different from the input duty cycle;
- a charge control device having a p-channel FET and blocking diodes, configured to selectively couple the charging device to deliver charge to the gate terminal, to selectively decouple the charging device from the gate terminal to charge the charging device, and to maintain charge on the gate terminal in response to decoupling the charging device from the gate terminal;
- a discharge control device having an n-channel FET, configured to selectively remove charge from the gate terminal and to selectively maintain charge on the gate terminal based on the input duty cycle;
- a charge pump having a first and a second n-channel FET configured to selectively charge the charging device, and a p-channel FET configured to increase a voltage of the charging device;
- and
- a timing device configured to generate the second duty cycle based on the input duty cycle.
An apparatus comprising:
- a high side FET;
- a low side FET that is coupled to the source of the high side FET at its drain;
- and
- a driver for the high side FET having:
- a first FET that receives a first drive signal at its gate;
- a second FET that is coupled to the drain of the first MOS transistor at its drain and that receives a clock signal at its gate;
- a third FET that receives an inverse of the clock signal at its gate;
- a capacitor that is coupled between the drain of the first MOS transistor and that source of the third FET transistor;
- a fourth FET that is coupled to the source of the third FET at its source, that is coupled to the gate of the high side FET at its drain, and that receives a second drive signal at its gate;
- and
- a fifth FET that is coupled to the drain of the fourth FET at its drain and that receives a data signal at its gate.
Dependencies are inferred from the claim text.