Skew tolerant communication between ratioed synchronous clocks

A method comprising:

• receiving a source clock signal;
• generating a first clock signal with a first frequency in a first clock domain, wherein the first clock signal is derived from the source clock signal;
• generating a second clock signal with a second frequency in a second clock domain, wherein the second clock signal is derived from the source clock signal, and wherein the second frequency is less than the first frequency;
• generating a pulse indicative of when data transferred between the first clock domain and the second clock domain may be latched;
• wherein said data is only latched when said pulse is asserted and on a given edge of the first clock signal, and wherein said method further comprises generating said pulse such that said given edge occurs at approximately a position corresponding to a middle of a period of the second clock signal;
• generating an additional pulse, wherein when said pulse is asserted and said additional pulse is not asserted, said data is always latched on a same edge of the first clock signal, either a positive edge or a negative edge.

An apparatus for use in a multiple clock domain system, the apparatus comprising:

• circuitry configured to generate a first clock signal derived from a source clock signal, wherein the first clock signal has a first frequency;
• and
• a pulse generation unit coupled to receive the first clock signal, wherein the pulse generation unit is configured to:
• repeatedly count a given number of cycles of the first clock signal;
• and
• generate a pulse indicative of when data being transferred between clock domains may be latched;
• wherein said data is only latched when said pulse is asserted and on a given edge of the first clock signal, and wherein said circuitry is configured to generate said pulse such that said given edge occurs at approximately a position corresponding to a middle of a period of the second clock signal;
• circuitry configured to generate an additional pulse, wherein when said pulse is asserted and said additional pulse is not asserted, said data is always latched on a same edge of the first clock signal, either a positive edge or a negative edge.

A data communications system comprising:

• a source clock signal;
• a first clock domain comprising a first clock signal which is derived from the source clock signal, wherein the first clock signal has a first frequency;
• a second clock domain comprising a second clock signal which is derived from the source clock signal, wherein the second clock signal has a second frequency which is less than the first frequency;
• and
• circuitry configured to generate a pulse indicative of when data transferred between the first clock domain and the second clock domain may be latched;
• wherein said data is only latched when said pulse is asserted and on a given edge of the first clock signal, and wherein said circuitry is configured to generate said pulse such that said given edge occurs at approximately a position corresponding to a middle of a period of the second clock signal;
• wherein said circuitry includes a sync pulse generator configured to generate said pulse, wherein said sync pulse generator includes a counter configured to repeatedly count a given number of cycles of the first clock signal and detect when selected counts occur;
• wherein a ratio of said first frequency to said second frequency is N:M, wherein said given number of cycles corresponds to N, and the number of selected counts detected corresponds to M;
• wherein said circuitry is further configured to detect selected values of the selected counts and generate an additional pulse in response thereto.

A method comprising:

• receiving a source clock signal;
• generating a first clock signal with a first frequency in a first clock domain, wherein the first clock signal is derived from the source clock signal;
• generating a second clock signal with a second frequency in a second clock domain, wherein the second clock signal is derived from the source clock signal, and wherein the second frequency is less than the first frequency;
• generating a pulse indicative of when data transferred between the first clock domain and the second clock domain may be latched;
• wherein said data is only latched when said pulse is asserted and on a given edge of the first clock signal, and wherein said method further comprises generating said pulse such that said given edge occurs at approximately a position corresponding to a middle of a period of the second clock signal;
• wherein generating said pulse comprise repeatedly counting a given number of cycles of the first clock signal and detecting when selected counts occur;
• wherein a ratio of said first frequency to said second frequency is N:M, wherein said given number of cycles corresponds to N, and the number of selected counts detected corresponds to M;
• and
• wherein further comprising detecting selected values of the selected counts and generating an additional pulse in response thereto.