Method and circuit for generating memory clock signal
AssigneeVIA Technologies, Inc.
InventorChi Chang
Life of this patent
Estimating the term…
Abstract
A memory clock signal is generated in response to a reference clock signal and a clock enable signal. The memory clock signal with a frequency identical to that of the reference clock signal is generated during the clock enable signal is in an enabled state; and the memory clock signal with a reduced frequency is generated when the clock enable signal is changed from the enabled state to a disabled state. The generation of a memory clock signal is adaptive so as to save power.
Claims14
A method of generating a memory clock signal for a memory in response to a reference clock signal and a clock enable signal, comprising:
- generating the memory clock signal with a frequency identical to that of the reference clock signal during an enabled state of the clock enable signal when data access to the memory is performed;
- and
- generating the memory clock signal with a reduced frequency when the clock enable signal is changed from the enabled state to a disabled state when no data access to the memory occurs.
A circuit for generating a memory clock signal for a memory, comprising:
- a clock generator generating a delayed clock enable signal according to a reference clock signal and a clock enable signal which is in an enabled state when data access to the memory is performed;
- a delay circuit coupled to the clock generator and including a series of interconnected latch units for generating a clock cycle selection signal according to an inverted reference clock signal having a phase inverse to the reference clock signal and the delayed clock enable signal;
- and
- a gating circuit coupled to the clock generator and the delay circuit for generating a gated memory clock signal according to the reference clock signal, the delayed clock enable signal and the clock cycle selection signal.
A circuit for generating a memory clock signal for a memory, comprising:
- a clock generator generating a delayed clock enable signal according to a reference clock signal and a clock enable signal which is in an enabled state when data access to the memory is performed;
- a delay circuit coupled to the clock generator and including a series of interconnected latch units for generating a clock cycle selection signal according to an inverted reference clock signal having a phase inverse to the reference clock signal and the delayed clock enable signal;
- and
- a gating circuit coupled to the clock generator and the delay circuit for generating a gated memory clock signal according to the reference clock signal, the delayed clock enable signal and the clock cycle selection signal;
- wherein the gating circuit includes:
- a first AND gate for operating the clock cycle selection signal and the reference clock signal to output a first signal;
- a second AND gate for operating the reference clock signal and a logic value “1” to output a second signal;
- a first NAND gate coupled to the first AND gate for operating the first signal and the delayed clock enable signal to output a third signal;
- a second NAND gate coupled to the second AND gate for operating the second signal and an inverted delayed clock enable signal to output a fourth signal;
- and
- a third NAND gate coupled to the first NAND gate and the second NAND gate for operating the third signal and the fourth signal to output the gated memory clock signal.
Dependencies are inferred from the claim text.