Method and apparatus for PLD having shared storage elements
AssigneeAltera Corporation
InventorsKeith Duwel, Michael D. Hutton
Life of this patent
Estimating the term…
Abstract
A programmable logic device (PLD) includes a core region having a plurality of logical array blocks (LABs). Each one of the plurality of logical array blocks include a plurality of logic elements capable of communicating with each other through interconnections defined within each logical array block. The logic elements include a look up table (LUT), wherein a LUT of a first logic element and a LUT of a second logic element share a register. In one embodiment, more than two logic elements may share a register. Thus, the embodiments provide for the ability to vary sequential logic, e.g., registers, instead of rigidly fixing the sequential logic and consequently the ratio of combinatorial logic to sequential logic.
Claims22
An integrated circuit, comprising:
- a core region having a plurality of logical array blocks, each of the plurality of logical array blocks include a plurality of logical elements configured to communicate with each other through interconnections defined within each logical array block, the logical elements each containing a look up table (LUT), wherein a LUT of a first logical element and a LUT of a second logical element share a register, and wherein each of the LUT of the first logical element and the LUT of the second logical element output data to a dedicated register.
A logic element (LE) for an integrated circuit, comprising:
- an input region for receiving inputs delivered to the LE;
- a look up table (LUT) region for manipulating data received from the input region, the LUT region including a plurality of look up tables;
- and
- a sequential region containing storage elements and control logic for storing output from the LUT region, wherein the sequential region includes a first storage element dedicated to the LUT region and a second storage element shared with the LUT region and a LUT region for another LE, the control logic including a first and a second multiplexer wherein each of the first and the second multiplexer employ an output from a corresponding logic gate as a selection signal.
A method for sharing a storage element between logical elements of an integrated circuit;
- comprising:
- receiving a plurality of inputs into a first lookup table (LUT) region of a first logic element;
- receiving a plurality of inputs into a second LUT region of a second logic element;
- combinatorially processing the plurality of inputs through corresponding lookup tables;
- transmitting output from the first LUT region to a storage element dedicated to the first logic element;
- transmitting output from the first LUT region to a storage element shared by the first logic element and the second logic element;
- and
- transmitting output from the second LUT region to a storage element dedicated to the second logic element.
Dependencies are inferred from the claim text.