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US 7,733,121 B2Granted
Methods and apparatus for programmably powering down structured application-specific integrated circuits
AssigneeAltera Corporation
InventorsHee Kong Phoon, Kar Keng Chua
Life of this patent
Estimating the term…
Abstract
Methods and apparatus for programmably powering down a structured application-specific integrated circuit are provided. At least one of the programmable layers of the structured ASIC that frequently provides some programmability as between or among a small number of alternative functions is used to provide this programmability.
Claims23
An integrated circuit device comprising:
- a plurality of base semiconductor layers;
- and
- a plurality of base metallization layers, wherein one of the base metallization layers comprises a first, second, and third portion, wherein the first and second portions each comprise conductive material, wherein the third portion includes a programmable metal element coupled to the first and second portions, wherein the first portion is configured to deliver power to a plurality of circuit blocks of the device, and wherein the second portion is configured to deliver the power from the first portion to circuitry only within one of the plurality of circuit blocks.
An integrated circuit device comprising:
- a plurality of base semiconductor layers;
- and
- a base metallization layer comprising a first portion, a second portion, and a third portion that form a hard circuit block, wherein the first and second portions each comprise conductive material, wherein the third portion includes a metal element coupled to the first portion and the second portion for powering down the hard circuit block, wherein the first portion is configured to deliver power to a plurality of circuit blocks of the device, and wherein the second portion is configured to deliver the power from the first portion to circuitry only within one of the plurality of circuit blocks.
An integrated circuit device comprising:
- a plurality of base semiconductor layers;
- and
- a base metallization layer with a hard circuit block comprising a global power line, a local power line, and a metal element coupled to the global power line and the local power line, wherein the metal element is configured to programmably power down the hard circuit block, wherein the global power line is configured to deliver power to a plurality of circuit blocks of the device, and wherein the local power line is configured to deliver the power from the global power line to circuitry only within one of the plurality of circuit blocks.
An integrated circuit device comprising:
- a plurality of base semiconductor layers;
- and
- a plurality of base metallization layers, wherein one of the base metallization layers comprises a first, second, third, and fourth portion, wherein the first and second portions each comprise conductive material, wherein the third portion includes a programmable metal element coupled to the first and second portions, wherein the base layers form at least one hard circuit block at a first location, and wherein the fourth portion is programmable for configuring the at least one hard circuit block.
An integrated circuit device comprising:
- a plurality of base semiconductor layers;
- and
- a base metallization layer comprising a first portion, a second portion, and a third portion that form a hard circuit block, wherein the first and second portions each comprise conductive material, wherein the third portion includes a metal element coupled to the first portion and the second portion for powering down the hard circuit block, wherein the base metallization layer further comprises a fourth portion, and wherein the fourth portion is programmable for configuring the hard circuit block.
Dependencies are inferred from the claim text.