Monitoring pattern for detecting a defect in a semiconductor device and method for detecting a defect
AssigneeSamsung Electronics Co., Ltd.
InventorsChoel-Hwyi Bae, Yong-Woon Han, Mi-Joung Lee, Sang-Deok Kwon
Life of this patent
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Abstract
A monitoring pattern for detecting a defect in a semiconductor device allows a voltage contrast inspection which may be verified by an electrical test where no special test pattern is required for the electrical test. The monitoring pattern includes a test pattern with line shapes arranged in parallel and spaced apart at predetermined linewidths and intervals, and an interconnection layer connected to the test pattern, where the test pattern is adapted to be charged with a specific potential to be displayed as a voltage contrast image when scanned with an electron beam.
Claims12
A monitoring pattern, comprising:
- a test pattern with a plurality of line shapes arranged in parallel and spaced apart at predetermined linewidths and intervals;
- and
- an interconnection layer connected to the test pattern,
- wherein the test pattern is adapted to be charged with a specific potential to be displayed as a voltage contrast image when scanned with an electron beam, and
- wherein the test pattern includes:
- a first pattern set including a plurality of grounded patterns,
- a second pattern set including a plurality of floating patterns, the grounded patterns and the floating patterns being alternately arranged, and
- at least one sub-pattern set between adjacent grounded and floating patterns, the sub-pattern set including a plurality of first sub-patterns extending in parallel from the grounded pattern and a plurality of second sub-patterns extending in parallel from the floating pattern.
A monitoring pattern, comprising:
- a test pattern with a plurality of line shapes arranged in parallel and spaced apart at predetermined linewidths and intervals;
- and
- an interconnection layer connected to the test pattern,
- wherein the test pattern is adapted to be charged with a specific potential to be displayed as a voltage contrast image when scanned with an electron beam, and
- wherein the test pattern includes:
- a first pattern set including a plurality of grounded patterns,
- a second pattern set including a plurality of floating patterns, the grounded patterns and the floating patterns being alternately arranged, and
- at least one sub-pattern between adjacent grounded and floating patterns, the sub-pattern including a plurality of parallel feature portions to connect the grounded pattern with the floating pattern.
A method for detecting a defect in a semiconductor device, comprising:
- forming a test pattern on a semiconductor substrate, the test pattern having a plurality of line shapes arranged in parallel at predetermined linewidths and predetermined intervals;
- scanning an electron beam over the test pattern to perform a voltage contrast inspection;
- connecting an interconnections to the test pattern;
- and
- measuring electrical continuity of the test pattern through the interconnections to verify the voltage contrast inspection,
- wherein forming the test pattern includes:
- forming a first pattern set including a plurality of grounded patterns,
- forming a second pattern set including a plurality of floating patterns, wherein the grounded patterns and the floating patterns are alternately arranged, and
- forming at least one sub-pattern set between adjacent grounded and floating patterns, the sub-pattern set including a plurality of first sub-patterns extending in parallel from the grounded pattern and a plurality of second sub-patterns extending in parallel from the floating pattern arranged alternately with the first sub-patterns.
Dependencies are inferred from the claim text.