Clock distribution circuit and test method

A clock distribution circuit having plural stages of buffers on a path for dividing up a clock signal, and configured in a manner that outputs of a plurality of buffers in a final stage and/or a middle stage are short-circuited, comprising:

• a first buffer and a second buffer respectively on a first path and a second path which branch off of each other at a branch node,
• a first switch for connecting and disconnecting between an output of the first buffer, and an input of a buffer in a subsequent stage or a flip-flop,
• a second switch for connecting and disconnecting between an output of the second buffer, and an input of a buffer in a subsequent stage or a flip-flop,
• a first selector which receives the output of the first buffer and a signal at the branch node respectively by a first input and a second input, and selects one of the first input and the second input to output, based on a select control signal, and
• an observation circuit for observing an output of the first selector.

A test method for a clock distribution circuit having plural stages of buffers along branch paths for dividing up and distributing a clock signal and configured in a manner that outputs of a plurality of buffers in a final stage and/or a middle stage are short-circuited, comprising:

• in relation to at least one buffer of a plurality of buffers in the same stage on a branch path, providing a selector which receives an output of an adjacent buffer located upstream in terms of a chain-connection along which the plurality of buffers are connected in testing, and a signal at a branch node corresponding to the one buffer by a first input and a second input respectively, selecting one of the first input and the second input, based on a select control signal, and supplying it to the one buffer;
• sequentially transferring an output of the one buffer down to a buffer at an ending point in the chain-connection through a selector and a buffer located downstream in the chain-connection, in a manner that the output of the one buffer is input to the first input of an adjacent selector located downstream in the chain-connection, then in the adjacent selector, the first input is selected, and the output of the one buffer is input to an adjacent buffer;
• and
• observing an output of the buffer at the ending point in the chain-connection.

A clock distribution network, comprising:

• a first path having a first buffer carrying clocking information originated from a clock source;
• a second path having a second buffer carrying clocking information originated from said clock source;
• and
• a third path coupled to said first and second buffers in sequence,
• said first and second paths being activated in common in a first mode of operation;
• and
• said third path being activated in a second mode of operation,
• wherein said third path is other than activated in said first mode of operation.