Voltage sensing in a supply regulator for a suspend mode
AssigneeXilinx, Inc.
InventorNarasimhan Vasudevan
Life of this patent
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Abstract
A voltage regulator for supplying power to volatile memory cells during a suspend mode of an integrated circuit is described. The integrated circuit in an awake mode generates a regulated voltage at an output node using a first supply voltage and in the suspend mode generates the regulated voltage at the output node using a second supply voltage, at less voltage than the first supply voltage. The second supply voltage is electrically decoupled from the output node for transitioning from the suspend mode to the awake mode, and the first supply voltage is electrically decoupled from the output node for transitioning from the awake mode to the suspend mode.
Claims20
A voltage regulator for supplying power to volatile memory cells, comprising:
- an amplifier coupled to receive a reference voltage and a regulated voltage and configured to provide a gating voltage;
- a first transistor coupled at a source node thereof to a first supply voltage and coupled at a gate thereof to receive the gating voltage;
- a second transistor coupled at a source node thereof to a second supply voltage;
- the second supply voltage having a logic high voltage level which is substantially less than that of the first supply voltage;
- the first transistor and the second transistor each having a drain node which is coupled at an output node;
- the regulated voltage being provided from the output node in part for a feedback input to the amplifier;
- the volatile memory cells being coupled to the output node for receiving the regulated voltage therefrom;
- control circuitry coupled to receive a first control signal and configured for providing control signaling, the control signaling including at least a second control signal;
- a third transistor coupled at a source node thereof to a ground potential and coupled at a gate thereof to receive the second control signal;
- a resistive load coupled to receive the first supply voltage;
- a drain node of the third transistor and the resistive load each coupled at a sense node;
- and
- the second transistor coupled at a gate thereof to receive a sense voltage obtained from the sense node.
A method for regulating voltage, comprising:
- toggling an integrated circuit between a suspend mode and an awake mode;
- in the awake mode, generating a regulated voltage at an output node using a first supply voltage, the first supply voltage having a first voltage level;
- in the suspend mode, generating the regulated voltage at the output node using a second supply voltage, the second supply voltage having a second voltage level which is substantially less than the first voltage level;
- inputting a reference voltage and the regulated voltage to an amplifier;
- producing a gating voltage from the amplifier;
- disabling the amplifier for bias circuit operation thereof for the suspend mode, wherein the gating voltage is provided from the amplifier at the first voltage level;
- and
- activating the amplifier for the bias circuit operation thereof for the awake mode, wherein the gating voltage is less than the first voltage level and greater than a regulated voltage level of the regulated voltage;
- electrically decoupling the second supply voltage from the output node for transitioning from the suspend mode to the awake mode;
- and
- electrically decoupling the first supply voltage from the output node for transitioning from the awake mode to the suspend mode.
Dependencies are inferred from the claim text.