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US 7,732,933 B2Granted
Semiconductor chip and TAB package having the same
AssigneeSamsung Electronics Co., Ltd.
InventorsYe-Chung Chung, Dong-Han Kim, Sa-Yoon Kang
Life of this patent
Estimating the term…
Abstract
A semiconductor chip, having an active surface including a peripheral area and a central area, presents a connection area formed on a portion of the peripheral area. The semiconductor chip includes output pads formed in the peripheral area of the active surface and input pads formed in the central area of the active surface. The input pads may be connected to wiring patterns of a TAB tape passing over the connection area.
Claims20
A TAB (Tape Automated Bonding) package comprising:
- a flexible film substrate;
- a plurality of wiring patterns including dedicated input patterns and dedicated output patterns disposed on the film substrate;
- and
- a semiconductor chip disposed on the film substrate, the semiconductor chip comprising:
- a major surface comprising two long sides and two short sides;
- a plurality of dedicated output bumps disposed on a peripheral area along the two long sides, the dedicated output bumps being coupled to corresponding dedicated output patterns;
- and
- a plurality of dedicated input bumps formed on the major surface and disposed between the dedicated output bumps, the dedicated input bumps being coupled to corresponding dedicated input patterns;
- wherein the dedicated input patterns pass over a first of the two long sides and extend toward a second of the two long sides as the dedicated input patterns run from an area outside the semiconductor chip to an area over the semiconductor chip,
- wherein at least one of the dedicated input patterns is connected to at least two dedicated input bumps, and
- wherein, in an area confined to above the major surface, a part of one the dedicated input patterns extends between and connects to at least two dedicated input bumps.
8 more elements
A TAB (Tape Automated Bonding) package comprising:
- a flexible film substrate;
- a plurality of wiring patterns including dedicated input patterns and dedicated output patterns disposed on the film substrate;
- a semiconductor chip mounted on the film substrate, the semiconductor chip having a major surface including two long sides and two short sides;
- a plurality of dedicated output bumps disposed on a peripheral area of the major surface and along at least one long side of the major surface, the dedicated output bumps being coupled to a corresponding dedicated output pattern;
- a dummy bump disposed along one long side of the major surface;
- and
- a plurality of dedicated input bumps, including a first dedicated input bump, disposed on the major surface, the dedicated input bumps being coupled to the dedicated input patterns,
- wherein the dedicated input patterns includes a first dedicated input pattern, the first dedicated input pattern being coupled to the dummy bump and the first dedicated input bump.
5 more elements
A TAB (Tape Automated Bonding) package comprising:
- a tape substrate;
- a plurality of leads formed on the tape substrate;
- a semiconductor chip including a plurality of terminals on a major surface of the semiconductor chip, the semiconductor chip being mounted to the tape substrate and connected to the plurality of leads via the plurality of terminals;
- wherein the plurality of terminals include at least a first group of terminals and a second group of terminals, the first group of terminals being spaced apart at a first pitch, and the second group of terminal being spaced apart at a second pitch different from the first pitch, wherein the second group of terminals includes at least one dummy terminal,
- wherein the second group of terminals includes two subgroups of second terminals and the at least one dummy terminal, wherein the at least one dummy terminal is positioned between the two subgroups of second terminals so that the second pitch is provided for all of the second terminals,
- wherein the terminals of the first group of terminals are consecutively arranged, the terminals of the second group of terminals are consecutively arranged, and the terminals of each of the two subgroups of second terminals are consecutively arranged.
3 more elements
Dependencies are inferred from the claim text.