Semiconductor chips with crack stop regions for reducing crack propagation from chip edges/corners

A semiconductor chip, comprising:

• (a) a semiconductor substrate;
• (b) a transistor on the semiconductor substrate;
• (c) N interconnect layers on top of the semiconductor substrate and the transistor, wherein N is a positive integer, and wherein the transistor is electrically coupled to the N interconnect layers;
• (d) a first dielectric layer on top of the N interconnect layers;
• (e) Q crack stop regions on top of the first dielectric layer, wherein Q is a positive integer;
• (f) a second dielectric layer on top of the first dielectric layer, wherein the first dielectric layer is sandwiched between the second dielectric layer and the N interconnect layers;
• and
• (g) an underfill layer on top of the second dielectric layer, wherein the second dielectric layer is sandwiched between the first dielectric layer and the underfill layer, and wherein each crack stop region of the Q crack stop regions is completely surrounded by the first dielectric layer and the underfill layer.

A semiconductor chip, comprising:

• (a) a semiconductor substrate;
• (b) a transistor on the semiconductor substrate;
• (c) N interconnect layers on top of the semiconductor substrate and the transistor, wherein N is a positive integer, and wherein the transistor is electrically coupled to the N interconnect layers;
• (d) a first dielectric layer on top of the N interconnect layers;
• (e) L trenches in a top interconnect layer of the N interconnect layers and the first dielectric layer, wherein L is a positive integer;
• (f) P crack stop regions and Q crack stop regions on top of the first dielectric layer, wherein P and Q are positive integers;
• (g) a second dielectric layer on top of the first dielectric layer, wherein the first dielectric layer is sandwiched between the second dielectric layer and the N interconnect layers, and wherein each crack stop region of the P crack stop regions is completely surrounded by the first dielectric layer and the second dielectric layer;
• and
• (h) an underfill layer on top of the second dielectric layer, wherein the second dielectric layer is sandwiched between the first dielectric layer and the underfill layer, wherein each crack stop region of the Q crack stop regions is completely surrounded by the first dielectric layer and the underfill layer, and wherein portions of the underfill layer completely fill the L trenches.

A chip fabrication method, comprising:

• providing a structure which includes:
• (a) a semiconductor substrate,
• (b) a transistor on the semiconductor substrate,
• (c) N interconnect layers on top of the semiconductor substrate and the transistor, wherein N is a positive integer, and wherein the transistor is electrically coupled to the N interconnect layers, and
• (d) a first dielectric layer on top of the N interconnect layers;
• forming P crack stop regions and Q crack stop regions on top of the first dielectric layer, wherein P and Q are positive integers;
• forming a second dielectric layer on top of the first dielectric layer, wherein the first dielectric layer is sandwiched between the second dielectric layer and the N interconnect layers, and wherein each crack stop region of the P crack stop regions is completely surrounded by the first dielectric layer and the second dielectric layer;
• and
• forming an underfill layer on top of the second dielectric layer, wherein the second dielectric layer is sandwiched between the first dielectric layer and the underfill layer, and wherein each crack stop region of the Q crack stop regions is completely surrounded by the first dielectric layer and the underfill layer.