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US 7,732,928 B2Granted
Structure for protecting electronic packaging contacts from stress
AssigneeInstrument Technology Research Center
InventorsShyh-Ming Chang, Ji-Cheng Lin, Shou-Lung Chen
Life of this patent
Estimating the term…
Abstract
A structure for protecting electronic package contacts is provided. The structure includes at least an electronic contact mounted on a chip, a dielectric layer, a conductor trace line and a protective layer. The protective layer is used to prevent stresses from being gathered within electronic contacts on the chip through surroundingly covering the conductor trace line.
Claims17
A structure for protecting an electronic packaging contact, comprising:
- a chip having at least an electrode;
- a first dielectric layer having a top surface consisting of a first surface and a second surface, and covering the chip without covering a via located over the electrode;
- a protecting layer entirely covering the first surface without covering the via and the second surface;
- a second dielectric layer covering the first dielectric layer without covering the via;
- wherein the protecting layer is embedded by, and partially surrounded by, the second dielectric layer, and the second surface is entirely in contact with the second dielectric layer;
- and
- a conductor trace line formed in the via, and partially surrounded by the protecting layer, and connected to the electrode for connecting electronic signals.
4 more elements
A structure for protecting an electronic packaging contact, comprising:
- a chip having at least an electrode;
- a substrate mounted on the chip for supporting and distracting heat from the chip;
- a first dielectric layer having a top surface consisting of a first surface and a second surface, and covering the chip without covering a via located over the electrode;
- a protecting layer entirely covering the first surface without covering the via and the second surface;
- a second dielectric layer covering the first dielectric layer without covering the via;
- wherein the protecting layer is embedded by, and partially surrounded by, the second dielectric layer, and the second surface is entirely in contact with the second dielectric layer;
- and
- a conductor trace line formed in the via, partially surrounded by the protecting layer, and connected to the electrode for connecting electronic signals.
5 more elements
A semiconductor structure, comprising:
- a chip having at least an electrode;
- a first dielectric layer having a top surface consisting of a first surface and a second surface, and covering the chip without covering a via located over the electrode;
- a protecting layer entirely covering the first surface without covering the via and the second surface;
- a second dielectric layer covering the first dielectric layer without covering the via, wherein the protecting layer is embedded by, and partially surrounded by, the second dielectric layer, and the second surface is entirely in contact with the second dielectric layer;
- and
- a conductor trace line formed in the via, partially surrounded by the protecting layer, and connected to the electrode for communicated electronic signals.
3 more elements
Dependencies are inferred from the claim text.