Semiconductor package substrate

A semiconductor package substrate comprising:

• a substrate body formed with a plurality of conductive through holes therein and a plurality of ball pads electrically connected to the conductive through holes, wherein at least two adjacent ones of the conductive through holes are formed as a differential pair;
• and
• at least one electrically integrated layer formed in the substrate body, and having an opening corresponding to the at least two conductive through holes and the ball pads, wherein the opening is sized large enough to completely cover the at least two conductive through holes and all of the ball pads, such that capacitance effects are controlled through adjustment of a spacing between the ball pads and the electrically integrated layer so as to maintain consistency between chip loop impedance and IC output impedance.