Back to results
US 7,732,908 B2Granted
Semiconductor device and semiconductor memory device
AssigneeKabushiki Kaisha Toshiba
InventorsTaku Nishiyama, Tetsuya Yamamoto, Kiyokazu Okada
Life of this patent
Estimating the term…
Abstract
A plurality of semiconductor elements configuring a first element group are stacked in a step-like shape on a wiring board. A plurality of semiconductor elements configuring a second element group are stacked in a step-like shape on the first element group toward a direction opposite to the stepped direction of the first element group. The semiconductor elements are electrically connected to connection pads of the wiring board through metallic wires. Among the plurality of semiconductor elements configuring the second element group, the lowermost semiconductor element has a thickness larger than those of the other semiconductor elements.
Claims20
A semiconductor device, comprising:
- a wiring board having a first surface provided with an element mounting section and connection pads, and a second surface on a side opposite to the first surface;
- a first element group including a plurality of semiconductor elements with electrode pads arranged along one outline side, the semiconductor elements being stacked in a step-like shape on the element mounting section of the wiring board with the outline sides directed to the same direction and the electrode pads exposed;
- a second element group including a plurality of semiconductor elements with electrode pads arranged along one outline side, the semiconductor elements being stacked in a step-like shape on the first element group in a direction opposite to the stepped direction of the first element group with the outline sides directed to the same direction and the electrode pads exposed;
- first metallic wires electrically connecting the electrode pads of the semiconductor elements configuring the first element group and the connection pads of the wiring board;
- second metallic wires electrically connecting the electrode pads of the semiconductor elements configuring the second element group and the connection pads of the wiring board;
- and
- a sealing resin layer formed on the first surface of the wiring board to seal the first and second element groups together with the first and second metallic wires,
- wherein the lowermost semiconductor element among the plurality of semiconductor elements configuring the second element group has a thickness larger than those of the other semiconductor elements among the plurality of semiconductor elements configuring the second element group.
5 more elements
A semiconductor device, comprising:
- a wiring board having a first surface provided with an element mounting section and connection pads, and a second surface on a side opposite to the first surface;
- a first element group including a plurality of first semiconductor elements with first electrode pads arranged along one outline side, the first semiconductor elements being stacked in a step-like shape on the element mounting section of the wiring board with the outline sides directed to the same direction and the first electrode pads exposed;
- a second element group including a plurality of second semiconductor elements with second electrode pads arranged along one outline side, the second semiconductor elements being stacked in a step-like shape on the first element group with the outline sides directed to the same direction and the second electrode pads exposed;
- first metallic wires electrically connecting the first electrode pads and the connection pads of the wiring board;
- second metallic wires electrically connecting the second electrode pads and the connection pads of the wiring board;
- and
- a sealing resin layer formed on the first surface of the wiring board to seal the first and second element groups together with the first and second metallic wires,
- wherein the second electrode pads are arranged on opposite faces of the second semiconductor elements from the wiring board, and a hollow portion filled with an insulating resin is arranged below the lowermost semiconductor element among the second semiconductor elements corresponding to second electrode pads of the lowermost semiconductor element.
5 more elements
A semiconductor memory device, comprising:
- a wiring board having a first surface provided with an element mounting section and connection pads, and a second surface on a side opposite to the first surface;
- external connection terminals formed on the second surface of the wiring board;
- a memory element group provided including a plurality of semiconductor memory elements with electrode pads arranged along one outline side, the semiconductor memory elements being stacked in a step-like shape on the element mounting section of the wiring board with the outline sides directed to the same direction and the electrode pads exposed;
- a controller element, stacked on the memory element group, having first electrode pads arranged along a first outline side and second electrode pads arranged along a second outline side orthogonal to the first outline side;
- a relay element stacked on the memory element group;
- first metallic wires electrically connecting the electrode pads of the semiconductor memory elements and the connection pads of the wiring board;
- second metallic wires electrically connecting the first electrode pads of the controller element and the connection pads of the wiring board;
- third metallic wires electrically connecting the second electrode pads of the controller element and the connection pads of the wiring board via the relay element;
- and
- a sealing resin layer formed on the first surface of the wiring board to seal the memory element group, the controller element and the relay element together with the first, second and third metallic wires.
7 more elements
A semiconductor memory device, comprising:
- a wiring board having a first surface provided with an element mounting section and connection pads, and a second surface on a side opposite to the first surface;
- external connection terminals formed on the second surface of the wiring board;
- a memory element group including a plurality of semiconductor memory elements with electrode pads arranged along one outline side, the semiconductor memory elements being stacked in a step-like shape on the element mounting section of the wiring board with the outline sides directed to the same direction and the electrode pads exposed;
- a controller element, arranged below an overhang portion of the semiconductor memory elements stacked in the step-like shape, flip-chip connecting to the connection pads of the wiring board;
- metallic wires electrically connecting the electrode pads of the semiconductor memory elements and the connection pads of the wiring board;
- and
- a sealing resin layer formed on the first surface of the wiring board to seal the memory element group and the controller element together with the metallic wires.
4 more elements
Dependencies are inferred from the claim text.