Multi-surface contact IC packaging structures and assemblies
AssigneeInterconnect Portfolio LLC
InventorsJoseph C. Fjelstad, Para K. Segaram, Thomas J. Obenhuber, Kevin P. Grundy, William F. Wiedemann
Life of this patent
Estimating the term…
Abstract
A cost effective, high performance, IC package assembly of the present invention comprises stair-stepped layers of redistribution circuits from at least one chip to terminals on any of multiple surfaces and levels of the IC package assembly. Critical path circuits of the assembly have no plated vias and are directly routed from interconnection terminals which are used to interconnect the package to the IC chip terminals by flip chip or wire bond methods.
Claims29
An integrated circuit (IC) package assembly for interconnecting and space transforming the I/O terminals from locations on a first IC die within the package assembly to I/O terminal locations distal from the first IC die, comprising:
- a first circuit layer having a first surface with a first plurality of conductive paths disposed thereupon, including a first conductive path extending from an interior IC package terminal disposed on a first exposed region of the first surface to an exterior IC package terminal disposed on a second exposed region of the first surface;
- and
- a second circuit layer having a second surface with a second plurality of conductive paths disposed thereupon, including a second conductive path extending from an interior IC terminal disposed on a first exposed region of the second surface to an exterior IC package terminal disposed on a second exposed region of the second surface, wherein a portion of the first conductive path is covered by the second circuit layer, the first exposed regions of the first and second surfaces are arranged in stair step structure, and the second exposed regions of the first and second surfaces are arranged in stair step structure.
An integrated circuit package assembly comprising:
- a first insulating substrate having first and second surfaces and a first outer edge extending from the first surface to the second surface and delimiting a first external dimension of the first insulating substrate;
- a first plurality of interior contacts disposed on an interior region of the second surface, and
- a first plurality of outer contacts disposed on the second surface proximate the first outer edge;
- a first plurality of conductive paths disposed on the second surface of the first insulating substrate, each of the first plurality of conductive paths extending from a respective one of the first plurality of interior contacts to a respective one of the first plurality of outer contacts;
- and
- a second insulating substrate having third and fourth surfaces, a first aperture extending from the third surface to the fourth surface, and a second outer edge extending from the third surface to the fourth surface and delimiting a second external dimension that is smaller than the first external dimension, wherein the third surface of the second insulating substrate is disposed against the second surface of the first insulating substrate and positioned such that the first plurality of interior contacts are positioned within a periphery of the first aperture, and such that the first plurality of outer contacts are not covered by the second insulating substrate, and at least a portion of each of the first conductive paths is covered by the second insulating substrate.
An integrated circuit (IC) package assembly comprising:
- a first substrate layer having an interior region and a peripheral region;
- a first plurality of signal paths that extend along a surface of the first substrate layer from signal path terminations in the interior region to signal path terminations in the peripheral region;
- and
- a second substrate layer disposed over the surface of the first substrate layer in an orientation that forms at least a portion of a first stepped profile at an edge of the IC package assembly and that exposes the signal path terminations in the peripheral region, the second substrate further comprising a first aperture to expose the interior region of the first substrate layer, wherein none of the first plurality of signal paths are in signal continuity with a plated through hole.
Dependencies are inferred from the claim text.