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US 7,732,899 B1Granted
Etch singulated semiconductor package
AssigneeAmkor Technology, Inc.
InventorsChristopher J. Berry, Christopher M. Scanlan, Faheem F. Faheem
Life of this patent
Estimating the term…
Abstract
In accordance with the present invention, there is provided various methods of simultaneously fabricating a plurality of semiconductor packages (e.g., cavity type semiconductor packages) wherein the singulation process is achieved using etching techniques as opposed to more conventional cutting techniques such as sawing or punching. Such etching techniques are inherently lower in cost and free from many of the defects induced by other cutting techniques.
Claims20
A semiconductor package, comprising:
- a die pad having opposed top and bottom surfaces and a peripheral edge;
- a plurality of leads disposed in spaced relation to the die pad, each of the leads having opposed top and bottom surfaces, an inner end and an outer end;
- plating layers applied to at least portions of the bottom surfaces of the die pad and the leads, each of the plating layers applied to the leads having an outer end;
- a semiconductor die attached to the die pad and electrically connected to at least some of the leads;
- and
- a package body having bottom and side surfaces, the package body at least partially encapsulating the die pad, the leads, the plating layers and the semiconductor die;
- the outer end of each of the leads being recessed relative to the outer end of the plating layer applied to the bottom surface thereof and to the side surface of the package body.
4 more elements
A semiconductor package, comprising:
- a plurality of leads, each of the leads having opposed top and bottom surfaces, an inner end and an outer end;
- plating layers applied to at least portions of the bottom surfaces of the leads, each of the plating layers having an outer end;
- a semiconductor die electrically connected to at least some of the leads;
- and
- a protective structure having bottom and side surfaces, the protective structure at least partially covering the leads, the plating layers, and the semiconductor die;
- the outer end of each of the leads being recessed relative to the outer end of the plating layer applied to the bottom surface thereof and to the side surface of the protective structure.
3 more elements
A semiconductor package, comprising:
- a plurality of leads, each of the leads having opposed top and bottom surfaces, and an outer end;
- plating layers applied to at least portions of the bottom surfaces of the leads, each of the plating layers having an outer end;
- a semiconductor die electrically connected to at least some of the leads;
- and
- a protective structure at least partially covering the leads, the plating layers, and the semiconductor die;
- the outer end of each of the leads being recessed relative to the outer end of the plating layer applied to the bottom surface thereof.
3 more elements
Dependencies are inferred from the claim text.