US 7,732,891 B2 · Semiconductor device

Abstract

A semiconductor device has a substrate, a source region formed on the surface portion of the substrate, a first insulating layer formed on the substrate, a gate electrode formed on the first insulating layer, a second insulating layer formed on the gate electrode, a body section connected with the source region, penetrating through the first insulating layer, the gate electrode and the second insulating layer, and containing a void, a gate insulating film surrounding the body section, and formed between the body section and the gate electrode, and a drain region connected with the body section.

Claims4

Dependent claims

A semiconductor device comprising:

a source region surrounded by a first insulating film;
a second insulating film formed on the first insulating film and the source region;
a plurality of third insulating films and gate electrodes alternately laminated on the second insulating film;
a body section connected with the source region, penetrating through the plurality of third insulating films, gate electrodes and the second insulating film, and containing a void;
a fourth insulating film surrounding the body section, having a charge accumulating ability formed between the body section and the gate electrode;
and
a drain region formed on the body section.

4 more elements

Dependencies are inferred from the claim text.

Facts

Application

12/132,181Filed 3 Jun 2008

Published

US 2009/0294844 A13 Dec 2009

Granted

8 Jun 2010

Term ends

Not estimatedThe source records don’t support an estimate.

Classification9 codes

H10D 30/69
Insulated-gate field-effect transistors [IGFET]: iGFETs having charge trapping gate insulators, e.g. MNOS transistors
H10B 43/20
EEPROM devices comprising charge-trapping gate insulators: characterised by three-dimensional [3D] arrangements, e.g. with cells on different…
H10B 43/27
With source and drain on different levels, e.g. with sloping channels: the channels comprising vertical portions, e.g. U-shaped channels
H10D 30/691
IGFETs having charge trapping gate insulators, e.g. MNOS transistors: having more than two programming levels

Semiconductor device

Life of this patent

Semiconductor device

Life of this patent

Abstract

Claims4